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Searched refs:REG_SEQ0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9611uxc.c662 REG_SEQ0(0x805a, 0x04), in lt9611uxc_firmware_write_page()
663 REG_SEQ0(0x805a, 0x00), in lt9611uxc_firmware_write_page()
665 REG_SEQ0(0x805e, 0xdf), in lt9611uxc_firmware_write_page()
666 REG_SEQ0(0x805a, 0x20), in lt9611uxc_firmware_write_page()
667 REG_SEQ0(0x805a, 0x00), in lt9611uxc_firmware_write_page()
668 REG_SEQ0(0x8058, 0x21), in lt9611uxc_firmware_write_page()
672 REG_SEQ0(0x805b, (addr >> 16) & 0xff), in lt9611uxc_firmware_write_page()
673 REG_SEQ0(0x805c, (addr >> 8) & 0xff), in lt9611uxc_firmware_write_page()
674 REG_SEQ0(0x805d, addr & 0xff), in lt9611uxc_firmware_write_page()
675 REG_SEQ0(0x805a, 0x10), in lt9611uxc_firmware_write_page()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs42l42.c2124 REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F),
2125 REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01),
2126 REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F),
2127 REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F),
2128 REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F),
2129 REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F),
2130 REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03),
2131 REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F),
2132 REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01),
2133 REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01),
[all …]
H A Dcs35l56-shared.c330 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
331 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
484 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW),
488 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
H A Dcs42l42-sdw.c430 REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e),
/openbmc/linux/drivers/power/supply/
H A Drt9471.c798 REG_SEQ0(RT9471_REG_INFO, 0x80), /* REG_RST */
799 REG_SEQ0(RT9471_REG_TOP, 0xC0), /* WDT = 0 */
800 REG_SEQ0(RT9471_REG_FUNC, 0x01), /* BATFET_DIS_DLY = 0 */
801 REG_SEQ0(RT9471_REG_IBUS, 0x0A), /* AUTO_AICR = 0 */
802 REG_SEQ0(RT9471_REG_VBUS, 0xC6), /* VAC_OVP = 14V */
803 REG_SEQ0(RT9471_REG_JEITA, 0x38), /* JEITA = 0 */
804 REG_SEQ0(RT9471_REG_DPDMDET, 0x31), /* BC12_EN = 0, DCP_DP_OPT = 1 */
/openbmc/linux/include/linux/
H A Dregmap.h100 #define REG_SEQ0(_reg, _def) REG_SEQ(_reg, _def, 0) macro