Searched refs:REG_RESET (Results 1 – 10 of 10) sorted by relevance
| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | lgs8gl5.c | 20 #define REG_RESET 0x02 macro
160 val = lgs8gl5_read_reg(state, REG_RESET); in lgs8gl5_soft_reset()
161 lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF); in lgs8gl5_soft_reset()
162 lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF); in lgs8gl5_soft_reset()
387 if (lgs8gl5_read_reg(state, REG_RESET) < 0) in lgs8gl5_attach()
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| /openbmc/u-boot/arch/sandbox/include/asm/ |
| H A D | rtc.h | 22 REG_RESET = 0x20, enumerator
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| /openbmc/linux/drivers/thunderbolt/ |
| H A D | nhi_regs.h | 115 #define REG_RESET 0x39898 macro
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| H A D | nhi.c | 1239 iowrite32(REG_RESET_HRR, nhi->iobase + REG_RESET); in nhi_reset()
1244 val = ioread32(nhi->iobase + REG_RESET); in nhi_reset()
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| /openbmc/linux/arch/mips/loongson2ef/lemote-2f/ |
| H A D | reset.c | 80 ec_write(REG_RESET, BIT_RESET_ON); in ml2f_reboot()
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| H A D | ec_kb3310b.h | 139 #define REG_RESET 0xF4EC macro
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| /openbmc/u-boot/drivers/rtc/ |
| H A D | sandbox_rtc.c | 74 return dm_i2c_reg_write(dev, REG_RESET, 0); in sandbox_rtc_reset()
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| H A D | i2c_rtc_emul.c | 199 if (offset == REG_RESET) in sandbox_i2c_rtc_xfer()
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| /openbmc/qemu/hw/ipack/ |
| H A D | tpci200.c | 54 #define REG_RESET 0x0A macro
222 case REG_RESET: in tpci200_read_las0()
264 case REG_RESET: in tpci200_write_las0()
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| /openbmc/qemu/hw/display/ |
| H A D | g364fb.c | 64 #define REG_RESET 0x100000 macro
422 case REG_RESET: in g364fb_ctrl_write()
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