Searched refs:REG_HDMITXPLL_DIV (Results 1 – 2 of 2) sorted by relevance
107 #define REG_HDMITXPLL_DIV GENMASK(4, 0) macro
203 mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1); in mtk_hdmi_pll_set_hw()