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Searched refs:REG_GET_3 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c84 regval = REG_GET_3(gpio.MASK_reg, in set_config()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c1234 REG_GET_3(DCN_SURF0_TTU_CNTL0, in hubp2_read_state_common()
1243 REG_GET_3(DCN_SURF1_TTU_CNTL0, in hubp2_read_state_common()
1276 REG_GET_3(DCHUBP_CNTL, in hubp2_read_state_common()
1575 REG_GET_3(DCN_SURF0_TTU_CNTL0, in hubp2_validate_dml_output()
1579 REG_GET_3(DCN_SURF1_TTU_CNTL0, in hubp2_validate_dml_output()
1583 REG_GET_3(DCN_CUR0_TTU_CNTL0, in hubp2_validate_dml_output()
H A Ddcn20_optc.c237 REG_GET_3(OPTC_DATA_SOURCE_SELECT, in optc2_get_optc_source()
H A Ddcn20_mpc.c491 REG_GET_3(MPCC_STATUS[mpcc_id], in mpc2_assert_mpcc_idle_before_connect()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.c489 REG_GET_3(DCN_SURF0_TTU_CNTL0, in hubp21_validate_dml_output()
493 REG_GET_3(DCN_SURF1_TTU_CNTL0, in hubp21_validate_dml_output()
497 REG_GET_3(DCN_CUR0_TTU_CNTL0, in hubp21_validate_dml_output()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c1001 REG_GET_3(DCN_SURF0_TTU_CNTL0, in hubp1_read_state_common()
1010 REG_GET_3(DCN_SURF1_TTU_CNTL0, in hubp1_read_state_common()
1043 REG_GET_3(DCHUBP_CNTL, in hubp1_read_state_common()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c697 REG_GET_3(DP_SYM32_ENC_VID_PIXEL_FORMAT, in dcn31_hpo_dp_stream_enc_read_state()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h165 #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ macro