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Searched refs:REG_GET (Results 1 – 25 of 106) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c706 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); in hubp2_dmdata_status_done()
881 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_enable_triplebuffer()
895 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_is_triplebuffer_enabled()
916 REG_GET(DCSURF_FLIP_CONTROL, in hubp2_is_flip_pending()
919 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp2_is_flip_pending()
922 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp2_is_flip_pending()
1121 REG_GET(HUBPRET_CONTROL, in hubp2_read_state_common()
1129 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, in hubp2_read_state_common()
1132 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, in hubp2_read_state_common()
1140 REG_GET(BLANK_OFFSET_1, in hubp2_read_state_common()
[all …]
H A Ddcn20_optc.c157 REG_GET(OPTC_DATA_FORMAT_CONTROL, in optc2_get_dsc_status()
290 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); in optc2_align_vblanks()
300 REG_GET(OTG_MASTER_UPDATE_LOCK, in optc2_align_vblanks()
306 REG_GET(OTG_V_BLANK_START_END, in optc2_align_vblanks()
308 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); in optc2_align_vblanks()
429 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); in optc2_lock_doublebuffer_enable()
431 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); in optc2_lock_doublebuffer_enable()
511 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate); in optc2_get_last_used_drr_vtotal()
H A Ddcn20_stream_encoder.c356 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
358 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state()
359 REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); in enc2_read_state()
361 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc2_read_state()
362 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc2_read_state()
364 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); in enc2_read_state()
365 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc2_read_state()
452 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc2_stream_encoder_update_dp_info_packets()
587 REG_GET(DIG_FIFO_STATUS, in enc2_get_fifo_cal_average_level()
H A Ddcn20_link_encoder.c193 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); in enc2_fec_is_active()
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
208 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); in link_enc2_read_state()
278 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); in dcn20_link_encoder_get_max_link_cap()
293 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); in dcn20_link_encoder_is_in_alt_mode()
H A Ddcn20_dsc.c153 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc2_read_state()
154 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc2_read_state()
155 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc2_read_state()
156 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc2_read_state()
157 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc2_read_state()
158 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc2_read_state()
159 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc2_read_state()
160 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); in dsc2_read_state()
235 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_enable()
260 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_disable()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c57 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dcn301_get_16_bit_backlight_from_pwm()
58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dcn301_get_16_bit_backlight_from_pwm()
60 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm); in dcn301_get_16_bit_backlight_from_pwm()
61 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dcn301_get_16_bit_backlight_from_pwm()
106 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dcn301_panel_cntl_hw_init()
134 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_panel_cntl_hw_init()
163 REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value); in dcn301_is_panel_backlight_on()
173 REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dcn301_is_panel_powered_on()
191 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_store_backlight_level()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
740 REG_GET(DCSURF_FLIP_CONTROL, in hubp1_is_flip_pending()
743 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp1_is_flip_pending()
746 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp1_is_flip_pending()
878 REG_GET(HUBPRET_CONTROL, in hubp1_read_state_common()
886 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, in hubp1_read_state_common()
889 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, in hubp1_read_state_common()
892 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, in hubp1_read_state_common()
895 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, in hubp1_read_state_common()
907 REG_GET(BLANK_OFFSET_1, in hubp1_read_state_common()
[all …]
H A Ddcn10_mpc.c152 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle()
153 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
154 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle()
166 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect()
398 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_mpc_init_single_inst()
425 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw()
429 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
430 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
431 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw()
445 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
[all …]
H A Ddcn10_optc.c660 REG_GET(OTG_STATUS_FRAME_COUNT, in optc1_get_vblank_counter()
701 REG_GET(OTG_NOM_VERT_POSITION, in optc1_get_position()
725 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, in optc1_did_triggered_reset_occur()
728 REG_GET(OTG_VERT_SYNC_CONTROL, in optc1_did_triggered_reset_occur()
752 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger()
1292 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye()
1329 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1336 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state()
1339 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
1342 REG_GET(OTG_V_TOTAL_MAX, in optc1_read_otg_state()
[all …]
H A Ddcn10_dpp.c99 REG_GET(DPP_CONTROL, in dpp_read_state()
101 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
103 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
105 REG_GET(CM_DGAM_CONTROL, in dpp_read_state()
107 REG_GET(CM_RGAM_CONTROL, in dpp_read_state()
109 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp_read_state()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.c88 REG_GET(VBLANK_PARAMETERS_5, in apply_DEDCN21_142_wa_for_hostvm_deadline()
96 REG_GET(VBLANK_PARAMETERS_6, in apply_DEDCN21_142_wa_for_hostvm_deadline()
104 REG_GET(FLIP_PARAMETERS_3, in apply_DEDCN21_142_wa_for_hostvm_deadline()
112 REG_GET(FLIP_PARAMETERS_4, in apply_DEDCN21_142_wa_for_hostvm_deadline()
265 REG_GET(HUBPRET_CONTROL, in hubp21_validate_dml_output()
358 REG_GET(BLANK_OFFSET_1, in hubp21_validate_dml_output()
360 REG_GET(DST_DIMENSIONS, in hubp21_validate_dml_output()
365 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp21_validate_dml_output()
391 REG_GET(VBLANK_PARAMETERS_1, in hubp21_validate_dml_output()
394 REG_GET(NOM_PARAMETERS_0, in hubp21_validate_dml_output()
[all …]
H A Ddcn21_hubbub.c78 REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active); in dcn21_dchvm_init()
628 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub21_wm_read_state()
631 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub21_wm_read_state()
634 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub21_wm_read_state()
637 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, in hubbub21_wm_read_state()
642 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub21_wm_read_state()
645 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, in hubbub21_wm_read_state()
648 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub21_wm_read_state()
651 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, in hubbub21_wm_read_state()
656 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub21_wm_read_state()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.c58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dce_get_16_bit_backlight_from_pwm()
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dce_get_16_bit_backlight_from_pwm()
62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in dce_get_16_bit_backlight_from_pwm()
63 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dce_get_16_bit_backlight_from_pwm()
99 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_panel_cntl_hw_init()
119 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_panel_cntl_hw_init()
153 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); in dce_is_panel_backlight_on()
166 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dce_is_panel_powered_on()
184 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_store_backlight_level()
H A Ddce_i2c_hw.c77 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status()
124 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply()
136 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); in is_engine_available()
140 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); in is_engine_available()
151 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
366 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hubbub.c54 REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, in dcn32_init_crb()
57 REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, in dcn32_init_crb()
60 REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, in dcn32_init_crb()
63 REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, in dcn32_init_crb()
66 REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, in dcn32_init_crb()
148 …ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segme… in dcn32_program_compbuf_size()
858 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub32_wm_read_state()
861 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub32_wm_read_state()
864 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub32_wm_read_state()
867 REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, in hubbub32_wm_read_state()
[all …]
H A Ddcn32_dio_stream_encoder.c406 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc32_read_state()
408 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); in enc32_read_state()
410 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc32_read_state()
411 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc32_read_state()
413 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); in enc32_read_state()
414 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc32_read_state()
435 REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on); in enc32_reset_fifo()
/openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn31.c68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn31_get_fb_base_offset()
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn31_get_fb_base_offset()
89 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn31_reset()
119 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); in dmub_dcn31_reset()
291 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); in dmub_dcn31_is_hw_init()
300 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn31_is_supported()
451 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn31_get_diagnostic_data()
454 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn31_get_diagnostic_data()
457 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn31_get_diagnostic_data()
460 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn31_get_diagnostic_data()
[all …]
H A Ddmub_dcn20.c72 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn20_get_fb_base_offset()
75 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn20_get_fb_base_offset()
100 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn20_reset()
352 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn20_is_hw_init()
361 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn20_is_supported()
457 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn20_get_diagnostic_data()
460 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn20_get_diagnostic_data()
463 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn20_get_diagnostic_data()
466 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn20_get_diagnostic_data()
469 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn20_get_diagnostic_data()
[all …]
H A Ddmub_dcn32.c69 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn32_get_fb_base_offset()
72 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn32_get_fb_base_offset()
90 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn32_reset()
315 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn32_is_hw_init()
324 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn32_is_supported()
456 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn32_get_diagnostic_data()
459 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn32_get_diagnostic_data()
462 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn32_get_diagnostic_data()
465 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn32_get_diagnostic_data()
468 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn32_get_diagnostic_data()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c493 REG_GET(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, in dcn31_hpo_dp_stream_enc_update_dp_info_packets()
535 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp0_enabled); in hpo_dp_is_gsp_enabled()
536 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp2_enabled); in hpo_dp_is_gsp_enabled()
537 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp3_enabled); in hpo_dp_is_gsp_enabled()
538 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL11, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp11_enabled); in hpo_dp_is_gsp_enabled()
690 REG_GET(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
692 REG_GET(DP_SYM32_ENC_VID_STREAM_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
694 REG_GET(DP_STREAM_ENC_INPUT_MUX_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
702 REG_GET(DP_SYM32_ENC_SDP_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
707 REG_GET(DP_STREAM_MAPPER_CONTROL0, in dcn31_hpo_dp_stream_enc_read_state()
[all …]
H A Ddcn31_dio_link_encoder.c615 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, in dcn31_link_encoder_is_in_alt_mode()
625 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, in dcn31_link_encoder_is_in_alt_mode()
628 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, in dcn31_link_encoder_is_in_alt_mode()
665 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, in dcn31_link_encoder_get_max_link_cap()
671 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, in dcn31_link_encoder_get_max_link_cap()
674 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, in dcn31_link_encoder_get_max_link_cap()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c59 REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on); in enc314_reset_fifo()
401 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc314_read_state()
403 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); in enc314_read_state()
405 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc314_read_state()
406 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc314_read_state()
408 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); in enc314_read_state()
409 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc314_read_state()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_stream_encoder.c395 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc3_read_state()
397 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc3_read_state()
398 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); in enc3_read_state()
400 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc3_read_state()
401 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc3_read_state()
403 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); in enc3_read_state()
404 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc3_read_state()
514 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc3_stream_encoder_update_dp_info_packets()
H A Ddcn30_dwb.c144 REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked); in dwb3_update()
177 REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled); in dwb3_is_enabled()
178 REG_GET(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, &fc_frame_capture_en); in dwb3_is_enabled()

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