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Searched refs:RCSR (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/sa1100/
H A Dcpu.c54 #define RCSR 0x04 macro
60 writel(0, RST_BASE + RCSR); in reset_cpu()
H A Dstart.S75 #define RCSR 0x04 macro
/openbmc/linux/arch/arm/mach-sa1100/
H A Dpm.c75 RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR; in sa11x0_pm_enter()
86 RCSR = RCSR_SMR; in sa11x0_pm_enter()
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa25x.c77 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; in pxa25x_cpu_pm_enter()
238 pxa_register_wdt(RCSR); in pxa25x_init()
H A Dpxa27x.c142 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; in pxa27x_cpu_pm_enter()
340 pxa_register_wdt(RCSR); in pxa27x_init()
H A Dpxa2xx.c25 RCSR = mask; in pxa2xx_clear_reset_status()
H A Dpxa2xx-regs.h32 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ macro
H A Dsharpsl_pm.c585 RCSR = 0x0f; in sharpsl_pm_resume()
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A Dreset.h15 RCSR = mask; in clear_reset_status()
H A DSA-1100.h1026 #define RCSR __REG(0x90030004) /* RC Status Reg. */ macro
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dpxa2xx.c242 rcsr = readl(RCSR); in pxa_wakeup()
243 writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR); in pxa_wakeup()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h1983 #define RCSR 0x40F00030 /* Reset Controller Status Register */ macro
/openbmc/u-boot/include/
H A DSA-1100.h1405 #define RCSR /* RC Status Reg. */ \ macro