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Searched refs:RCS0 (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c50 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
51 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
52 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
53 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
[all …]
H A Dscheduler.c101 if (workload->engine->id != RCS0) in sr_oa_regs()
165 if (workload->engine->id == RCS0) { in populate_shadow_context()
218 if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0) in populate_shadow_context()
505 if (workload->engine->id == RCS0 && in intel_gvt_scan_and_shadow_workload()
977 if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0) in update_guest_context()
1703 if (engine->id == RCS0) { in intel_vgpu_create_workload()
H A Dexeclist.c49 [RCS0] = RCS_AS_CONTEXT_SWITCH,
H A Dcmd_parser.c425 #define R_RCS BIT(RCS0)
597 [RCS0] = {
1051 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) { in cmd_handler_lri()
1152 [RCS0] = {
H A Dhandlers.c326 engine_mask |= BIT(RCS0); in gdrst_mmio_write()
2081 id = RCS0; in gvt_reg_tlb_control_handler()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_pci.c93 .platform_engine_mask = BIT(RCS0), \
108 .platform_engine_mask = BIT(RCS0), \
140 .platform_engine_mask = BIT(RCS0), \
203 .platform_engine_mask = BIT(RCS0), \
231 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
239 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
245 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
271 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
319 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
387 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
[all …]
H A Di915_irq.c1020 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i8xx_irq_handler()
1127 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i915_irq_handler()
1252 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], in i965_irq_handler()
H A Di915_drv.h717 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
H A Di915_gpu_error.c1298 case RCS0: in engine_record_registers()
/openbmc/linux/drivers/gpu/drm/i915/selftests/
H A Dmock_gem_device.c232 to_gt(i915)->engine[RCS0] = mock_engine(i915, "mock", RCS0); in mock_gem_device()
233 if (!to_gt(i915)->engine[RCS0]) in mock_gem_device()
236 if (mock_engine_init(to_gt(i915)->engine[RCS0])) in mock_gem_device()
H A Di915_request.c218 ce = i915_gem_context_get_engine(ctx[0], RCS0); in igt_request_rewind()
236 ce = i915_gem_context_get_engine(ctx[1], RCS0); in igt_request_rewind()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_engine_cs.c148 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in perf_mi_bb_start()
275 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in perf_mi_noop()
H A Dselftest_gt_pm.c103 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in live_gt_clocks()
H A Dintel_engine_cs.c64 [RCS0] = {
403 [RCS0] = GEN11_GRDOM_RENDER, in get_reset_domain()
436 [RCS0] = GEN6_GRDOM_RENDER, in get_reset_domain()
1706 [RCS0] = MSG_IDLE_CS, in __cs_pending_mi_force_wakes()
1789 if (engine->id != RCS0) in intel_engine_get_instdone()
1823 if (engine->id != RCS0) in intel_engine_get_instdone()
1835 if (engine->id == RCS0) in intel_engine_get_instdone()
H A Dintel_engine_types.h112 RCS0 = 0, enumerator
H A Dintel_engine_user.c167 [RENDER_CLASS] = { RCS0, 1 }, in legacy_ring_idx()
H A Dintel_ring_submission.c93 case RCS0: in set_hwsp()
940 GEM_BUG_ON(engine->id != RCS0); in switch_context()
H A Dintel_mocs.c620 [RCS0] = __GEN9_RCS0_MOCS0, in mocs_offset()
H A Dgen8_engine_cs.c171 case RCS0: in gen12_get_aux_inv_reg()
H A Dintel_execlists_submission.c3502 [RCS0] = GEN8_RCS_IRQ_SHIFT, in logical_ring_default_irqs()
/openbmc/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2232 if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) { in i915_reset_gen7_sol_offsets()
2479 [I915_EXEC_DEFAULT] = RCS0,
2480 [I915_EXEC_RENDER] = RCS0,
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_overlay.c1397 engine = to_gt(dev_priv)->engine[RCS0]; in intel_overlay_setup()