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Searched refs:RCC_MP_APB1ENSETR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/st/stm32mp1/
H A Dboard.c18 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) in board_debug_uart_init() macro
22 setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); in board_debug_uart_init()
/openbmc/linux/drivers/clk/stm32/
H A Dclk-stm32mp13.c165 CFG_GATE_SETCLR(GATE_TIM2, RCC_MP_APB1ENSETR, 0),
166 CFG_GATE_SETCLR(GATE_TIM3, RCC_MP_APB1ENSETR, 1),
167 CFG_GATE_SETCLR(GATE_TIM4, RCC_MP_APB1ENSETR, 2),
168 CFG_GATE_SETCLR(GATE_TIM5, RCC_MP_APB1ENSETR, 3),
169 CFG_GATE_SETCLR(GATE_TIM6, RCC_MP_APB1ENSETR, 4),
170 CFG_GATE_SETCLR(GATE_TIM7, RCC_MP_APB1ENSETR, 5),
171 CFG_GATE_SETCLR(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9),
172 CFG_GATE_SETCLR(GATE_SPI2, RCC_MP_APB1ENSETR, 11),
173 CFG_GATE_SETCLR(GATE_SPI3, RCC_MP_APB1ENSETR, 12),
174 CFG_GATE_SETCLR(GATE_USART3, RCC_MP_APB1ENSETR, 15),
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H A Dstm32mp13_rcc.h123 #define RCC_MP_APB1ENSETR 0x700 macro
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c103 #define RCC_MP_APB1ENSETR 0xA00 macro
509 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
510 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
511 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
512 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
515 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
517 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
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