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Searched refs:PMSELR_EL0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/arm/
H A Dcpregs.h523 FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
590 FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
750 DO_BIT(HDFGRTR, PMSELR_EL0),
/openbmc/linux/arch/arm64/kvm/
H A Dsys_regs.c854 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; in access_pmselr()
857 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) in access_pmselr()
926 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) in access_pmu_evcntr()
977 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; in access_pmu_evtyper()
2238 { PMU_SYS_REG(PMSELR_EL0),
2239 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
H A Demulate-nested.c1448 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1),
/openbmc/linux/Documentation/arch/arm64/
H A Dperf.rst129 In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is
/openbmc/linux/arch/arm64/include/asm/
H A Dkvm_host.h322 PMSELR_EL0, /* Event Counter Selection Register */ enumerator
/openbmc/linux/arch/arm64/tools/
H A Dsysreg2206 Field 19 PMSELR_EL0
2270 Field 19 PMSELR_EL0