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Searched refs:PLL_MODE_MASK (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/clk/spear/
H A Dclk-vco-pll.c45 #define PLL_MODE_MASK 3 macro
199 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; in clk_vco_recalc_rate()
242 val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); in clk_vco_set_rate()
243 val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT; in clk_vco_set_rate()
/openbmc/linux/include/linux/mfd/
H A Didt82p33_reg.h55 #define PLL_MODE_MASK (0x1F) macro
H A Didt8a340_reg.h515 #define PLL_MODE_MASK (0x7) macro
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3368.h74 PLL_MODE_MASK = GENMASK(9, 8), enumerator
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c70 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { in rkclk_pll_get_rate()
100 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, in rkclk_set_pll()
122 rk_clrsetreg(&pll->con3, PLL_MODE_MASK, in rkclk_set_pll()
H A Dclk_rk3399.c90 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, enumerator
332 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
353 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
/openbmc/linux/arch/mips/ar7/
H A Dclock.c54 #define PLL_MODE_MASK 0x00000001 macro
191 if ((pll & PLL_MODE_MASK) == 0) in tnetd7300_get_clock()
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-pll.c20 #define PLL_MODE_MASK 0x3 macro
1092 pll_mux->mask = PLL_MODE_MASK; in rockchip_clk_register_pll()
/openbmc/linux/drivers/ptp/
H A Dptp_clockmatrix.c1387 *mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK; in idtcm_get_pll_mode()
1405 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); in idtcm_set_pll_mode()
H A Dptp_idt82p33.c114 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); in idt82p33_dpll_set_mode()