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Searched refs:PLLE_SS_CNTL_BYPASS_SS (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c625 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
712 PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
743 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c654 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
758 PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
789 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c939 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
990 PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
1027 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1125 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
1228 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c70 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) macro
75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
1670 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); in clk_plle_tegra114_enable()
2513 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); in clk_plle_tegra210_enable()