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Searched refs:PLLE_BASE_ENABLE (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c630 #define PLLE_BASE_ENABLE (1 << 30) macro
685 value &= ~PLLE_BASE_ENABLE; in tegra_plle_enable()
716 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c659 #define PLLE_BASE_ENABLE (1 << 30) macro
714 value &= ~PLLE_BASE_ENABLE; in tegra_plle_enable()
762 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c943 #define PLLE_BASE_ENABLE (1 << 30) macro
1005 value |= PLLE_BASE_ENABLE; in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1129 #define PLLE_BASE_ENABLE (1 << 31) macro
1199 value |= PLLE_BASE_ENABLE; in tegra_plle_enable()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c57 #define PLLE_BASE_ENABLE BIT(31) macro
2445 return val & PLLE_BASE_ENABLE ? 1 : 0; in clk_plle_tegra210_is_enabled()
2500 val |= PLLE_BASE_ENABLE; in clk_plle_tegra210_enable()
2542 val &= ~PLLE_BASE_ENABLE; in clk_plle_tegra210_disable()