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Searched refs:PLL3 (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/sound/soc/codecs/
H A Dak4642.c113 #define PLL3 (1 << 7) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
363 pll = PLL3; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/openbmc/linux/include/dt-bindings/clock/
H A Dstm32mp13-clks.h21 #define PLL3 8 macro
H A Dstm32mp1-clks.h185 #define PLL3 178 macro
H A Dqcom,gcc-ipq806x.h231 #define PLL3 222 macro
H A Dqcom,gcc-mdm9615.h288 #define PLL3 278 macro
H A Dqcom,gcc-msm8960.h286 #define PLL3 278 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clks.h185 #define PLL3 178 macro
/openbmc/linux/drivers/media/dvb-frontends/
H A Dzl10039.c42 PLL3, enumerator
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs55 PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
/openbmc/u-boot/drivers/video/tegra124/
H A Dsor.c564 DUMP_REG(PLL3); in dump_sor_reg()
705 tegra_sor_write_field(sor, PLL3, in tegra_dc_sor_enable_dp()
H A Dsor.h282 #define PLL3 0x1a macro
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt25 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi169 <&gcc PLL3>,
H A Dqcom-apq8064.dtsi853 <&gcc PLL3>,
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dhw.c740 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
742 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
756 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
H A Dreg.h1375 #define PLL3 0x16188 macro
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-msm8960.c3242 [PLL3] = &pll3.clkr,
3470 [PLL3] = &pll3.clkr,
H A Dgcc-ipq806x.c3069 [PLL3] = &pll3.clkr,
/openbmc/linux/drivers/clk/
H A Dclk-stm32mp1.c1775 PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),