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Searched refs:PIR_CLRSR (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c286 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
313 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
319 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c301 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); in phy_init()
330 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC in memory_init()
436 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
441 PIR_CLRSR); in data_training()
H A Dsdram_rk3288.c359 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); in phy_init()
388 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC in memory_init()
494 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
499 PIR_CLRSR); in data_training()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sunxi_dw.h185 #define PIR_CLRSR (0x1 << 27) /* clear status registers */ macro
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dddr_rk3288.h285 #define PIR_CLRSR (1 << 28) macro
H A Dsdram_rk322x.h345 #define PIR_CLRSR BIT(28) macro