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Searched refs:PIPE_FIFO_UNDERRUN_STATUS (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_fifo_underrun.c102 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
106 intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
126 enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_set_fifo_underrun_reporting()
129 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
H A Dintel_display_irq.c205 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | in i915_pipestat_enable_mask()
405 PIPE_FIFO_UNDERRUN_STATUS); in i9xx_pipestat_irq_reset()
436 status_mask = PIPE_FIFO_UNDERRUN_STATUS; in i9xx_pipestat_irq_ack()
489 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i8xx_pipestat_irq_handler()
510 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_pipestat_irq_handler()
534 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_pipestat_irq_handler()
560 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_reg.h2592 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) macro