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Searched refs:PDIV (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S257 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
266 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c127 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); in board_clock_init()
128 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); in board_clock_init()
211 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); in board_clock_init()
H A Dsetup.h12 #define PDIV(x) (((x) & 0x3f) << 8) macro
/openbmc/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c47 #define PDIV(val) FIELD_GET(GENMASK(5, 0), val) macro
710 return DIV_ROUND_CLOSEST_ULL(rate, PDIV(val1)); in rzg2l_cpg_pll_clk_recalc_rate()
/openbmc/qemu/hw/misc/
H A Dbcm2835_cprman.c82 pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); in pll_update()
/openbmc/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h70 FIELD(A2W_PLLx_CTRL, PDIV, 12, 3)