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Searched refs:PCLK_PWM0 (Results 1 – 14 of 14) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3368-cru.h137 #define PCLK_PWM0 350 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dpx30-cru.h162 #define PCLK_PWM0 339 macro
H A Drk3368-cru.h134 #define PCLK_PWM0 350 macro
H A Drk3308-cru.h185 #define PCLK_PWM0 206 macro
H A Drockchip,rv1126-cru.h48 #define PCLK_PWM0 35 macro
H A Drk3568-cru.h61 #define PCLK_PWM0 48 macro
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi493 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
504 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
515 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
526 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
H A Drk356x.dtsi461 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
472 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
483 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
494 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
H A Dpx30.dtsi670 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3368.c704 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
H A Dclk-rk3308.c874 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
H A Dclk-px30.c856 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
H A Dclk-rv1126.c318 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
H A Dclk-rk3568.c1507 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,