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Searched refs:PCC0_RBASE (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h136 #define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) macro
179 #define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT))
199 #define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT))
200 #define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT))
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dclock.c274 writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C)); in init_clk_rgpio2p()