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Searched refs:PAD_RETENTION_DRAM_COREBLK_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h705 #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 macro
H A Ddmc_init_ddr3.c668 writel(PAD_RETENTION_DRAM_COREBLK_VAL, in ddr3_mem_ctrl_init()