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Searched refs:OPC_SUB (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc198 OPC_SUB = 0x40000033,
1097 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
1375 tcg_out_opc_reg(s, OPC_SUB, ret, TCG_REG_ZERO, tmp);
2045 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
2110 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c214 OPC_SUB = 0x22 | OPC_SPECIAL, enumerator
2539 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB in gen_arith()
2582 case OPC_SUB: in gen_arith()
13241 case OPC_SUB: in decode_opc_special()
H A Dmicromips_translate.c.inc1684 mips32_op = OPC_SUB;
H A Dnanomips_translate.c.inc1299 gen_arith(ctx, OPC_SUB, rd, rs, rt);