Searched refs:NDCR (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | marvell_nand.c | 125 #define NDCR 0x00 macro
521 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_int()
522 writel_relaxed(reg | int_mask, nfc->regs + NDCR); in marvell_nfc_disable_int()
530 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_int()
531 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); in marvell_nfc_enable_int()
559 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_force_byte_access()
566 writel_relaxed(ndcr, nfc->regs + NDCR); in marvell_nfc_force_byte_access()
579 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, in marvell_nfc_wait_ndrun()
584 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_wait_ndrun()
585 nfc->regs + NDCR); in marvell_nfc_wait_ndrun()
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| /openbmc/linux/arch/arm/mach-pxa/ |
| H A D | pxa3xx.c | 51 #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0)) macro
419 NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL; in pxa3xx_init()
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 39 #define NDCR (0x00) /* Control register */ macro
569 nand_writel(info, NDCR, 0); in pxa3xx_nand_start()
570 nand_writel(info, NDCR, ndcr); in pxa3xx_nand_start()
577 ndcr = nand_readl(info, NDCR); in disable_int()
578 nand_writel(info, NDCR, ndcr | int_mask); in disable_int()
1467 uint32_t ndcr = nand_readl(info, NDCR); in pxa3xx_nand_detect_config()
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| /openbmc/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 2334 #define NDCR 0x43100000 /* Data Flash Control register */ macro
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