| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
35 tristate "Amstrad E3 NAND controller"
39 Support for NAND flash on Amstrad E3 (Delta).
[all …]
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 2 menuconfig NAND config
3 bool "Raw NAND Device Support"
4 if NAND
10 NAND initialization process.
19 bool "Support Atmel NAND controller"
22 Enable this driver for NAND flash platforms using an Atmel NAND
64 bool "Support TI Davinci NAND controller"
66 Enable this driver for NAND flash controllers available in TI Davinci
75 bool "Support Denali NAND controller as a DT device"
79 Enable the driver for NAND flash on platforms using a Denali NAND
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | pinmux.c | 137 PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
138 PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4),
139 PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4),
140 PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4),
141 PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4),
142 PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV),
143 PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV),
144 PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4),
145 PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT),
146 PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4),
[all …]
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| /openbmc/u-boot/doc/ |
| H A D | README.nand-boot-ppc440 | 2 NAND boot on PPC440 platforms
5 This document describes the U-Boot NAND boot feature as it
8 The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
9 completely without NOR FLASH. This can be done by using the NAND
10 boot feature of the 440 NAND flash controller (NDFC).
16 Will load first 4k from NAND (SPL) into cache and execute it from there.
20 Will load special U-Boot version (NUB) from NAND and execute it. This SPL
22 controller and the NAND controller so that the special U-Boot image can be
23 loaded from NAND to SDRAM.
26 c) NUB (NAND U-Boot)
[all …]
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| H A D | README.nand | 2 NAND FLASH commands and notes
16 Print information about the current NAND device.
41 Print information about all of the NAND devices found.
44 Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
50 `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
55 Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
67 the NAND flash in a manner identical to the 'nand write' command
70 NAND flash. This behaviour is required when flashing UBI images
77 corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
83 Read or write one or more pages at "ofs" in NAND flash, from or to
[all …]
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| /openbmc/u-boot/configs/ |
| H A D | chiliboard_defconfig | 31 …NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-sp…
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| H A D | ti816x_evm_defconfig | 34 …NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-sp…
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| H A D | am43xx_evm_rtconly_defconfig | 25 …NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-sp…
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| H A D | am43xx_hs_evm_defconfig | 35 …NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-sp…
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| H A D | am43xx_evm_usbhost_boot_defconfig | 36 …NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-sp…
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| H A D | am335x_hs_evm_defconfig | 29 …NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-sp…
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| H A D | am43xx_evm_defconfig | 29 …NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-sp…
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| H A D | am335x_evm_defconfig | 28 …NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-sp…
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| H A D | am335x_hs_evm_uart_defconfig | 31 …NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-sp…
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | pinmux.c | 140 PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
142 PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV),
143 PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE),
144 PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE),
145 PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB),
146 PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC),
147 PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE),
148 PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT),
149 PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE),
150 PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4),
[all …]
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| /openbmc/linux/drivers/mtd/nand/raw/brcmnand/ |
| H A D | Kconfig | 2 tristate "Broadcom STB NAND controller"
6 Enables the Broadcom NAND controller driver. The controller was
13 tristate "Broadcom BCM63xx NAND controller glue"
16 Enables the BRCMNAND glue driver to register the NAND controller
20 tristate "Broadcom BCMA NAND controller"
29 tristate "Broadcom BCMBCA NAND controller glue"
32 Enables the BRCMNAND glue driver to register the NAND controller
39 Enables the BRCMNAND glue driver to register the NAND controller
43 tristate "Broadcom iProc NAND controller glue"
46 Enables the BRCMNAND controller glue driver to register the NAND
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| /openbmc/u-boot/board/phytec/pcm058/ |
| H A D | README | 5 The SOM is sold in two versions, with eMMC or with NAND. Support
6 here is for the SOM with NAND.
23 The SOM can boot from NAND or from SD-Card, having the SPI-NOR
26 NAND and SD.
28 DIP-1 set to off: Boot first from NAND, then try SPI
34 device where SPL was loaded (SD or SPI). Booting from NAND is
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| /openbmc/u-boot/doc/device-tree-bindings/nand/ |
| H A D | nvidia,tegra20-nand.txt | 1 NAND Flash
9 The device node for a NAND flash device is as follows:
17 Nvidia NAND Controller
20 The device node for a NAND flash controller is as follows:
26 nvidia,nand-width : bus width of the NAND device in bits
28 - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
41 Optional child node of NAND chip nodes:
|
| H A D | fsmc-nand.txt | 2 NAND Interface
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
|
| H A D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
24 the GPIO's and the NAND flash data bus. If present, then after changing
|
| H A D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
36 1st entry: the CS line this NAND chip is connected to
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
64 SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
[all …]
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| /openbmc/linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra30.c | 2194 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, …
2219 …PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, …
2220 …PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, …
2221 …PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, …
2222 …PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, …
2223 …PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, …
2224 …PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, …
2225 …PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, …
2226 …PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, …
2227 …PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, …
[all …]
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| /openbmc/u-boot/board/freescale/mpc8313erdb/ |
| H A D | README | 18 To boot the image at the beginning of NAND flash, use these
28 When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
38 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
44 When booting from NAND, NAND flash is CS0 and NOR flash
67 NAND_33 - 33 MHz oscillator, boot from NAND flash
68 NAND_66 - 66 MHz oscillator, boot from NAND flash)
86 NAND flash:
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| /openbmc/u-boot/board/ti/am335x/ |
| H A D | README | 23 worth noting that aside from things such as NAND or MMC only being
38 define additional text blocks (such as for NAND or DFU strings). Also
43 NAND
46 The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
47 this example to program the NAND we assume that an SD card has been
50 into memory, then written to NAND.
52 Step-1: Building u-boot for NAND boot
53 Set following CONFIGxx options for NAND device.
54 CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
55 CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
[all …]
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