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Searched refs:M_REG_NUM_BANKS (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/arm/
H A Dcpu.h543 uint32_t vecbase[M_REG_NUM_BANKS];
544 uint32_t basepri[M_REG_NUM_BANKS];
545 uint32_t control[M_REG_NUM_BANKS];
546 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
547 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
551 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
554 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
556 uint32_t primask[M_REG_NUM_BANKS];
557 uint32_t faultmask[M_REG_NUM_BANKS];
560 uint32_t csselr[M_REG_NUM_BANKS];
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H A Dcpu-qom.h60 M_REG_NUM_BANKS = 2, enumerator
H A Dmachine.c430 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
472 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
473 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
484 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
485 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
486 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
487 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/openbmc/qemu/include/hw/arm/
H A Darmv7m.h73 SysTickState systick[M_REG_NUM_BANKS];
/openbmc/qemu/include/hw/intc/
H A Darmv7m_nvic.h58 uint32_t prigroup[M_REG_NUM_BANKS];
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c2730 M_REG_NUM_BANKS); in armv7m_nvic_instance_init()