| /openbmc/linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8qm-lvds-phy.c | 22 #define M_MASK GENMASK(18, 17) macro
23 #define M(n) FIELD_PREP(M_MASK, (n))
39 #define CTRL_INIT_MASK (M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | RFB)
117 regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val); in mixel_lvds_phy_power_on()
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| /openbmc/u-boot/include/bedbug/ |
| H A D | tables.h | 133 { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
135 { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
137 { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
139 { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
141 { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
143 { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
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| H A D | ppc.h | 271 #define M_MASK M_OPCODE(0x3f,0x1) macro
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| /openbmc/linux/drivers/atm/ |
| H A D | iphase.c | 314 #define M_MASK 0x1ff in cellrate_to_float() macro
326 flot = NZ | (i << M_BITS) | (cr & M_MASK); in cellrate_to_float()
328 flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK); in cellrate_to_float()
330 flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK); in cellrate_to_float()
345 mantissa = rate & M_MASK;
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| /openbmc/linux/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 2461 #define M_MASK M (0x3f, 1) macro
2471 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2474 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
4587 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4588 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4590 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4591 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4595 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4596 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4599 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
[all …]
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| /openbmc/linux/drivers/iommu/ |
| H A D | msm_iommu_hw-8xxx.h | 1123 #define M (M_MASK << M_SHIFT)
1585 #define M_MASK 0x01 macro
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