Searched refs:MX6QDL_PAD_EIM_LBA__GPIO2_IO27 (Results 1 – 15 of 15) sorted by relevance
105 /* MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 */
352 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
296 #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 macro
413 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0
239 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */
625 #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 macro
354 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1
380 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1
347 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */
443 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */
454 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */
610 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1
1212 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
300 #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 macro
629 #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 macro