Searched refs:MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 (Results 1 – 15 of 15) sorted by relevance
266 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0
327 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000
322 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
413 #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 macro
202 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */
444 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
154 #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 macro
301 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */
620 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */
627 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */
492 fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
835 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
1161 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
417 #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 macro
158 #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 macro