Searched refs:MTL_GSC_HECI2_BASE (Results 1 – 3 of 3) sorted by relevance
282 intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE), in intel_gsc_proxy_request_handler()318 intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE), in i915_gsc_proxy_component_bind()343 intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE), in i915_gsc_proxy_component_unbind()
742 HECI_H_GS1(MTL_GSC_HECI2_BASE), in wa_14015076503_start()747 HECI_H_CSR(MTL_GSC_HECI2_BASE), in wa_14015076503_start()762 HECI_H_GS1(MTL_GSC_HECI2_BASE), in wa_14015076503_end()
932 #define MTL_GSC_HECI2_BASE 0x00117000 macro