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Searched refs:MSR_IA32_TSX_CTRL (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/arch/x86/kernel/cpu/
H A Dtsx.c27 rdmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
40 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
47 rdmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
59 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
122 rdmsrl(MSR_IA32_TSX_CTRL, msr); in tsx_clear_cpuid()
124 wrmsrl(MSR_IA32_TSX_CTRL, msr); in tsx_clear_cpuid()
/openbmc/linux/arch/x86/power/
H A Dcpu.c485 { MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL }, in pm_save_spec_msr()
/openbmc/linux/Documentation/arch/x86/
H A Dtsx_async_abort.rst107 indicates whether MSR_IA32_TSX_CTRL is supported.
/openbmc/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h183 #define MSR_IA32_TSX_CTRL 0x00000122 macro
/openbmc/linux/arch/x86/include/asm/
H A Dmsr-index.h198 #define MSR_IA32_TSX_CTRL 0x00000122 macro
/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dtsx_async_abort.rst181 parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used
/openbmc/linux/arch/x86/kvm/vmx/
H A Dvmx.c1899 vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM)); in vmx_setup_uret_msrs()
2014 case MSR_IA32_TSX_CTRL: in vmx_get_msr()
2313 case MSR_IA32_TSX_CTRL: in vmx_set_msr()
7496 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL); in vmx_vcpu_create()
7812 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL); in vmx_vcpu_after_set_cpuid()
8425 MSR_IA32_TSX_CTRL, in vmx_setup_user_return_msrs()
/openbmc/linux/arch/x86/kvm/
H A Dcpuid.c1563 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && in kvm_cpuid()
H A Dx86.c1457 MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL,
7203 case MSR_IA32_TSX_CTRL: in kvm_probe_msr_to_save()
/openbmc/qemu/target/i386/kvm/
H A Dkvm.c2563 case MSR_IA32_TSX_CTRL: in kvm_get_supported_msrs()
3929 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl); in kvm_put_msrs()
4410 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0); in kvm_get_msrs()
4892 case MSR_IA32_TSX_CTRL: in kvm_get_msrs()
/openbmc/qemu/target/i386/
H A Dcpu.h410 #define MSR_IA32_TSX_CTRL 0x122 macro