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Searched refs:MSCC_PATCH_RAM_ADDR (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/net/phy/
H A Dmscc.c141 #define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2) macro
366 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
625 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
820 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1), in vsc8574_config_pre_init()
/openbmc/linux/drivers/net/phy/mscc/
H A Dmscc.h218 #define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2) macro
H A Dmscc_main.c923 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
1027 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
1222 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1498 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); in vsc8584_config_pre_init()
2051 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); in vsc8514_config_pre_init()