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Searched refs:MP1_BASE__INST0_SEG4 (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c42 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h465 #define MP1_BASE__INST0_SEG4 0 macro
H A Dnavi10_ip_offset.h523 #define MP1_BASE__INST0_SEG4 0 macro
H A Ddimgrey_cavefish_ip_offset.h710 #define MP1_BASE__INST0_SEG4 0x02400400 macro
H A Dnavi12_ip_offset.h703 #define MP1_BASE__INST0_SEG4 0x02400400 macro
H A Dnavi14_ip_offset.h703 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
H A Dvega20_ip_offset.h550 #define MP1_BASE__INST0_SEG4 0 macro
H A Dsienna_cichlid_ip_offset.h710 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
H A Dbeige_goby_ip_offset.h837 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
H A Drenoir_ip_offset.h953 #define MP1_BASE__INST0_SEG4 0x00F00000 macro
H A Dvega10_ip_offset.h369 #define MP1_BASE__INST0_SEG4 0 macro
H A Dvangogh_ip_offset.h960 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
H A Dyellow_carp_offset.h879 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
H A Darct_ip_offset.h698 #define MP1_BASE__INST0_SEG4 0x00EC0000 macro
H A Daldebaran_ip_offset.h1007 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro