| /openbmc/u-boot/board/xilinx/zynqmp/ |
| H A D | tap_delays.c | 59 #define MMC_TIMING_UHS_DDR50 4 macro
150 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
158 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
170 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
178 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
220 case MMC_TIMING_UHS_DDR50: in arasan_zynqmp_set_tapdelay()
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | xenon_sdhci.c | 103 #define MMC_TIMING_UHS_DDR50 7 macro
234 (priv->timing == MMC_TIMING_UHS_DDR50) || in xenon_mmc_phy_set()
344 priv->timing = MMC_TIMING_UHS_DDR50; in xenon_sdhci_set_ios_post()
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | sdhci-of-arasan.c | 749 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sdcardclk_set_phase()
818 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sampleclk_set_phase()
878 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sdcardclk_set_phase()
945 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sampleclk_set_phase()
1112 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()
1319 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, in arasan_dt_parse_clk_phases()
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| H A D | dw_mmc-starfive.c | 36 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
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| H A D | dw_mmc-hi3798cv200.c | 33 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
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| H A D | sdhci-pxav3.c | 266 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()
279 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
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| H A D | sdhci-xenon.c | 214 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()
359 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
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| H A D | rtsx_pci_sdmmc.c | 1036 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1117 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
1337 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()
1352 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
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| H A D | sdhci-xenon-phy.c | 650 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()
784 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
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| H A D | sdhci-pci-arasan.c | 284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
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| H A D | sdhci-st.c | 291 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
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| H A D | sdhci-brcmstb.c | 119 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_brcmstb_set_uhs_signaling()
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| H A D | sdhci-esdhc-imx.c | 1109 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
1227 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()
1314 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
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| H A D | usdhi6rol0.c | 750 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()
853 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()
860 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
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| H A D | sdhci-omap.c | 830 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()
1153 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
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| H A D | dw_mmc-exynos.c | 335 case MMC_TIMING_UHS_DDR50: in dw_mci_exynos_set_ios()
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| H A D | sunxi-mmc.c | 741 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()
891 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
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| H A D | rtsx_usb_sdmmc.c | 1060 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1124 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
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| H A D | sdhci-of-dwcmshc.c | 180 else if ((timing == MMC_TIMING_UHS_DDR50) || in dwcmshc_set_uhs_signaling()
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| H A D | owl-mmc.c | 524 if (ios->timing == MMC_TIMING_UHS_DDR50) { in owl_mmc_set_ios()
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| H A D | mmci_stm32_sdmmc.c | 302 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) in mmci_sdmmc_set_clkreg()
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| /openbmc/linux/include/linux/mmc/ |
| H A D | host.h | 60 #define MMC_TIMING_UHS_DDR50 7 macro
637 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
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| /openbmc/linux/drivers/mmc/core/ |
| H A D | debugfs.c | 141 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
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| H A D | sd.c | 498 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()
670 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()
681 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
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| H A D | host.c | 256 &map->phase[MMC_TIMING_UHS_DDR50]); in mmc_of_parse_clk_phase()
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