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Searched refs:MMC_TIMING_MMC_DDR52 (Results 1 – 25 of 41) sorted by relevance

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/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-hi3798cv200.c32 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_hi3798cv200_set_ios()
40 if (ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_hi3798cv200_set_ios()
H A Dsdhci-of-arasan.c750 case MMC_TIMING_MMC_DDR52: in sdhci_zynqmp_sdcardclk_set_phase()
819 case MMC_TIMING_MMC_DDR52: in sdhci_zynqmp_sampleclk_set_phase()
879 case MMC_TIMING_MMC_DDR52: in sdhci_versal_sdcardclk_set_phase()
946 case MMC_TIMING_MMC_DDR52: in sdhci_versal_sampleclk_set_phase()
1000 case MMC_TIMING_MMC_DDR52: in sdhci_versal_net_emmc_sdcardclk_set_phase()
1046 case MMC_TIMING_MMC_DDR52: in sdhci_versal_net_emmc_sampleclk_set_phase()
1321 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, in arasan_dt_parse_clk_phases()
H A Ddw_mmc-rockchip.c49 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
107 case MMC_TIMING_MMC_DDR52: in dw_mci_rk3288_set_ios()
H A Ddw_mmc-starfive.c36 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
H A Dsdhci-xenon.c215 (timing == MMC_TIMING_MMC_DDR52)) in xenon_set_uhs_signaling()
360 host->timing == MMC_TIMING_MMC_DDR52) in xenon_execute_tuning()
H A Dsdhci-xenon-phy.c651 case MMC_TIMING_MMC_DDR52: in xenon_emmc_phy_set()
783 case MMC_TIMING_MMC_DDR52: in xenon_hs_delay_adj()
H A Dsdhci-omap.c830 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()
1173 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; in sdhci_omap_config_iodelay_pinctrl_state()
1179 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; in sdhci_omap_config_iodelay_pinctrl_state()
H A Dsdhci-pci-arasan.c283 case MMC_TIMING_MMC_DDR52: in arasan_select_phy_clock()
H A Dsdhci-sprd.c111 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
362 case MMC_TIMING_MMC_DDR52: in sdhci_sprd_set_uhs_signaling()
H A Dsunxi-mmc.c742 ios->timing != MMC_TIMING_MMC_DDR52) { in sunxi_mmc_clk_set_phase()
787 if (ios->timing == MMC_TIMING_MMC_DDR52 && in sunxi_mmc_clk_set_rate()
892 ios->timing == MMC_TIMING_MMC_DDR52) in sunxi_mmc_set_clk()
H A Dsdhci_am654.c131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
684 if (i <= MMC_TIMING_MMC_DDR52) in sdhci_am654_get_otap_delay()
H A Dsdhci-of-at91.c105 if (timing == MMC_TIMING_MMC_DDR52) { in sdhci_at91_set_uhs_signaling()
H A Dsdhci-st.c292 case MMC_TIMING_MMC_DDR52: in sdhci_st_set_uhs_signaling()
H A Dsdhci-brcmstb.c120 (timing == MMC_TIMING_MMC_DDR52)) in sdhci_brcmstb_set_uhs_signaling()
H A Dsdhci-cadence.c304 case MMC_TIMING_MMC_DDR52: in sdhci_cdns_set_uhs_signaling()
H A Dsdhci-pxav3.c265 case MMC_TIMING_MMC_DDR52: in pxav3_set_uhs_signaling()
H A Dmeson-gx-mmc.c568 case MMC_TIMING_MMC_DDR52: in meson_mmc_prepare_ios_clock()
588 case MMC_TIMING_MMC_DDR52: in meson_mmc_check_resampling()
H A Ddw_mmc-exynos.c324 case MMC_TIMING_MMC_DDR52: in dw_mci_exynos_set_ios()
H A Dsdhci-of-dwcmshc.c181 (timing == MMC_TIMING_MMC_DDR52)) in dwcmshc_set_uhs_signaling()
/openbmc/u-boot/drivers/mmc/
H A Dxenon_sdhci.c104 #define MMC_TIMING_MMC_DDR52 8 macro
236 (priv->timing == MMC_TIMING_MMC_DDR52)) { in xenon_mmc_phy_set()
358 priv->timing = MMC_TIMING_MMC_DDR52; in xenon_sdhci_set_ios_post()
/openbmc/linux/drivers/mmc/core/
H A Dhost.h73 return card->host->ios.timing == MMC_TIMING_MMC_DDR52; in mmc_card_ddr52()
H A Ddebugfs.c144 case MMC_TIMING_MMC_DDR52: in mmc_ios_show()
H A Dhost.c258 &map->phase[MMC_TIMING_MMC_DDR52]); in mmc_of_parse_clk_phase()
/openbmc/u-boot/board/xilinx/zynqmp/
H A Dtap_delays.c62 #define MMC_TIMING_MMC_DDR52 7 macro
/openbmc/linux/include/linux/mmc/
H A Dhost.h61 #define MMC_TIMING_MMC_DDR52 8 macro

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