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Searched refs:MLX5_CAP_GEN (Results 1 – 25 of 105) sorted by relevance

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/openbmc/linux/drivers/infiniband/hw/mlx5/
H A Dumr.h30 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) in mlx5r_umr_can_load_pas()
37 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && in mlx5r_umr_can_load_pas()
55 MLX5_CAP_GEN(dev->mdev, atomic) && in mlx5r_umr_can_reconfig()
56 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) in mlx5r_umr_can_reconfig()
60 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && in mlx5r_umr_can_reconfig()
61 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) in mlx5r_umr_can_reconfig()
65 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || in mlx5r_umr_can_reconfig()
66 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) && in mlx5r_umr_can_reconfig()
67 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) in mlx5r_umr_can_reconfig()
H A Dmain.c109 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); in mlx5_ib_port_link_layer()
529 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); in mlx5_query_port_roce()
647 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) in mlx5_use_mad_ifc()
648 return !MLX5_CAP_GEN(dev->mdev, ib_virt); in mlx5_use_mad_ifc()
744 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, in mlx5_query_max_pkeys()
828 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); in mlx5_ib_query_device()
863 if (MLX5_CAP_GEN(mdev, pkv)) in mlx5_ib_query_device()
865 if (MLX5_CAP_GEN(mdev, qkv)) in mlx5_ib_query_device()
867 if (MLX5_CAP_GEN(mdev, apm)) in mlx5_ib_query_device()
869 if (MLX5_CAP_GEN(mdev, xrc)) in mlx5_ib_query_device()
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H A Dcounters.c203 return MLX5_CAP_GEN(dev->mdev, q_counter_other_vport) && in vport_qcounters_supported()
204 MLX5_CAP_GEN(dev->mdev, q_counter_aggregation); in vport_qcounters_supported()
399 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { in do_get_hw_stats()
603 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { in mlx5_ib_fill_counters()
613 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { in mlx5_ib_fill_counters()
623 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { in mlx5_ib_fill_counters()
633 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) { in mlx5_ib_fill_counters()
643 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { in mlx5_ib_fill_counters()
696 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) in __mlx5_ib_alloc_counters()
701 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) in __mlx5_ib_alloc_counters()
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H A Dqp.c326 if (!MLX5_CAP_GEN(dev->mdev, qpc_extension) || in mlx5_ib_qp_err_syndrome()
327 !MLX5_CAP_GEN(dev->mdev, qp_error_syndrome)) in mlx5_ib_qp_err_syndrome()
440 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) in set_rq_size()
475 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { in set_rq_size()
478 MLX5_CAP_GEN(dev->mdev, in set_rq_size()
605 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { in calc_sq_size()
607 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); in calc_sq_size()
617 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { in calc_sq_size()
621 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); in calc_sq_size()
644 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { in set_user_buf_size()
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H A Dumr.c55 if (MLX5_CAP_GEN(dev->mdev, atomic)) in get_umr_update_access_mask()
58 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) in get_umr_update_access_mask()
61 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) in get_umr_update_access_mask()
79 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) in umr_check_mkey_mask()
83 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) in umr_check_mkey_mask()
87 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) in umr_check_mkey_mask()
91 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) in umr_check_mkey_mask()
384 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || in mlx5r_umr_set_access_flags()
685 return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled); in umr_can_use_indirect_mkey()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dsf.h11 return MLX5_CAP_GEN(dev, sf_base_id); in mlx5_sf_start_function_id()
18 return MLX5_CAP_GEN(dev, sf); in mlx5_sf_supported()
25 if (MLX5_CAP_GEN(dev, max_num_sf)) in mlx5_sf_max_functions()
26 return MLX5_CAP_GEN(dev, max_num_sf); in mlx5_sf_max_functions()
28 return 1 << MLX5_CAP_GEN(dev, log_max_sf); in mlx5_sf_max_functions()
H A Dclock.h38 u8 rq_ts_format_cap = MLX5_CAP_GEN(mdev, rq_ts_format); in mlx5_is_real_time_rq()
47 u8 sq_ts_format_cap = MLX5_CAP_GEN(mdev, sq_ts_format); in mlx5_is_real_time_sq()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dfw.c150 if (MLX5_CAP_GEN(dev, port_selection_cap)) { in mlx5_query_hca_caps()
156 if (MLX5_CAP_GEN(dev, hca_cap_2)) { in mlx5_query_hca_caps()
162 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { in mlx5_query_hca_caps()
169 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { in mlx5_query_hca_caps()
176 if (MLX5_CAP_GEN(dev, pg)) { in mlx5_query_hca_caps()
182 if (MLX5_CAP_GEN(dev, atomic)) { in mlx5_query_hca_caps()
188 if (MLX5_CAP_GEN(dev, roce)) { in mlx5_query_hca_caps()
194 if (MLX5_CAP_GEN(dev, nic_flow_table) || in mlx5_query_hca_caps()
195 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { in mlx5_query_hca_caps()
212 if (MLX5_CAP_GEN(dev, qos)) { in mlx5_query_hca_caps()
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H A Dvport.c271 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list) : in mlx5_query_nic_vport_mac_list()
272 1 << MLX5_CAP_GEN(dev, log_max_current_mc_list); in mlx5_query_nic_vport_mac_list()
330 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list) : in mlx5_modify_nic_vport_mac_list()
331 1 << MLX5_CAP_GEN(dev, log_max_current_mc_list); in mlx5_modify_nic_vport_mac_list()
381 max_list_size = 1 << MLX5_CAP_GEN(dev, log_max_vlan_list); in mlx5_modify_nic_vport_vlans()
471 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) in mlx5_modify_nic_vport_node_guid()
531 is_group_manager = MLX5_CAP_GEN(dev, vport_group_manager); in mlx5_query_hca_vport_gid()
532 tbsz = mlx5_get_gid_table_len(MLX5_CAP_GEN(dev, gid_table_size)); in mlx5_query_hca_vport_gid()
565 if (MLX5_CAP_GEN(dev, num_ports) == 2) in mlx5_query_hca_vport_gid()
598 is_group_manager = MLX5_CAP_GEN(dev, vport_group_manager); in mlx5_query_hca_vport_pkey()
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H A Den_dcbnl.c60 #define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \
92 if (!MLX5_CAP_GEN(priv->mdev, dcbx)) in mlx5e_dcbnl_switch_to_host_mode()
117 if (!MLX5_CAP_GEN(priv->mdev, ets)) in mlx5e_dcbnl_ieee_getets()
328 if (!MLX5_CAP_GEN(priv->mdev, ets)) in mlx5e_dcbnl_ieee_setets()
424 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) { in mlx5e_dcbnl_setdcbx()
456 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) || in mlx5e_dcbnl_ieee_setapp()
509 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) || in mlx5e_dcbnl_ieee_delapp()
631 if (!MLX5_CAP_GEN(mdev, ets)) in mlx5e_dcbnl_setall()
740 if (!MLX5_CAP_GEN(priv->mdev, ets)) { in mlx5e_dcbnl_getpgtccfgtx()
1028 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos)) in mlx5e_dcbnl_build_netdev()
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H A Duar.c63 if (MLX5_CAP_GEN(mdev, uar_4k)) in uars_per_sys_page()
64 return MLX5_CAP_GEN(mdev, num_of_uars_per_page); in uars_per_sys_page()
73 if (MLX5_CAP_GEN(mdev, uar_4k)) in uar2pfn()
201 (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) + MLX5_BF_OFFSET; in map_offset()
281 bf_reg_size = 1 << MLX5_CAP_GEN(dev, log_bf_reg_size); in addr_to_dbi_in_syspage()
H A Dpci_irq.c68 min_msix = MLX5_CAP_GEN(dev, min_dynamic_vf_msix_table_size); in mlx5_get_default_msix_vec_count()
69 max_msix = MLX5_CAP_GEN(dev, max_dynamic_vf_msix_table_size); in mlx5_get_default_msix_vec_count()
100 if (!MLX5_CAP_GEN(dev, vport_group_manager) || !mlx5_core_is_pf(dev)) in mlx5_set_msix_vec_count()
103 min_msix = MLX5_CAP_GEN(dev, min_dynamic_vf_msix_table_size); in mlx5_set_msix_vec_count()
104 max_msix = MLX5_CAP_GEN(dev, max_dynamic_vf_msix_table_size); in mlx5_set_msix_vec_count()
766 int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? in mlx5_irq_table_create()
767 MLX5_CAP_GEN(dev, max_num_eqs) : in mlx5_irq_table_create()
768 1 << MLX5_CAP_GEN(dev, log_max_eq); in mlx5_irq_table_create()
778 pcif_vec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + 1; in mlx5_irq_table_create()
H A Den_common.c42 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); in mlx5e_mkey_set_relaxed_ordering()
43 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read) || in mlx5e_mkey_set_relaxed_ordering()
45 MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled)); in mlx5e_mkey_set_relaxed_ordering()
H A Ddevlink.c421 if (new_state && !MLX5_CAP_GEN(dev, roce) && in mlx5_devlink_enable_roce_validate()
422 !(MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))) { in mlx5_devlink_enable_roce_validate()
479 if (val32 > BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))) { in mlx5_devlink_hairpin_queue_size_validate()
482 BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))); in mlx5_devlink_hairpin_queue_size_validate()
508 MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))); in mlx5_devlink_hairpin_params_init_values()
534 value.vbool = MLX5_CAP_GEN(dev, roce) && !mlx5_dev_is_lightweight(dev); in mlx5_devlink_set_params_init_values()
764 value.vu32 = 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list); in mlx5_devlink_max_uc_list_params_register()
H A Ddev.c64 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_eth_supported()
67 if (!MLX5_CAP_GEN(dev, eth_net_offloads)) { in mlx5_eth_supported()
72 if (!MLX5_CAP_GEN(dev, nic_flow_table)) { in mlx5_eth_supported()
105 if (!MLX5_CAP_GEN(dev, cq_moderation)) in mlx5_eth_supported()
172 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in is_mp_supported()
H A Dmain.c224 if (!MLX5_CAP_GEN(dev, driver_version)) in mlx5_set_driver_version()
440 if (!MLX5_CAP_GEN(dev, atomic)) in handle_hca_cap_atomic()
470 !MLX5_CAP_GEN(dev, pg)) in handle_hca_cap_odp()
540 return MLX5_CAP_GEN(dev, roce); in mlx5_is_roce_on()
586 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), in handle_hca_cap()
649 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) in handle_hca_cap()
677 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || in is_roce_fw_disabled()
678 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); in is_roce_fw_disabled()
715 if (!MLX5_CAP_GEN(dev, port_selection_cap)) in handle_hca_cap_port_selection()
814 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) in mlx5_core_set_hca_defaults()
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H A Deq.c312 if (!param->mask[0] && MLX5_CAP_GEN(dev, log_max_uctx)) in create_map_eq()
557 if (MLX5_CAP_GEN(dev, general_notification_event)) in gather_async_events_mask()
560 if (MLX5_CAP_GEN(dev, port_module_event)) in gather_async_events_mask()
568 if (MLX5_CAP_GEN(dev, fpga)) in gather_async_events_mask()
574 if (MLX5_CAP_GEN(dev, temp_warn_event)) in gather_async_events_mask()
580 if (MLX5_CAP_GEN(dev, max_num_of_monitor_counters)) in gather_async_events_mask()
599 if (MLX5_CAP_GEN(dev, event_cap)) in gather_async_events_mask()
1199 max_dev_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? in get_num_eqs()
1200 MLX5_CAP_GEN(dev, max_num_eqs) : in get_num_eqs()
1201 1 << MLX5_CAP_GEN(dev, log_max_eq); in get_num_eqs()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/diag/
H A Dreporter_vnic.c40 if (MLX5_CAP_GEN(dev, vnic_env_queue_counters)) { in mlx5_reporter_vnic_diagnose_counters()
53 if (MLX5_CAP_GEN(dev, eq_overrun_count)) { in mlx5_reporter_vnic_diagnose_counters()
65 if (MLX5_CAP_GEN(dev, vnic_env_cq_overrun)) { in mlx5_reporter_vnic_diagnose_counters()
72 if (MLX5_CAP_GEN(dev, invalid_command_count)) { in mlx5_reporter_vnic_diagnose_counters()
79 if (MLX5_CAP_GEN(dev, quota_exceeded_count)) { in mlx5_reporter_vnic_diagnose_counters()
86 if (MLX5_CAP_GEN(dev, nic_receive_steering_discard)) { in mlx5_reporter_vnic_diagnose_counters()
94 if (MLX5_CAP_GEN(dev, vnic_env_cnt_steering_fail)) { in mlx5_reporter_vnic_diagnose_counters()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dmonitor_stats.c27 if (!MLX5_CAP_GEN(mdev, max_num_of_monitor_counters)) in mlx5e_monitor_counter_supported()
30 MLX5_CAP_GEN(mdev, num_ppcnt_monitor_counters) < in mlx5e_monitor_counter_supported()
33 if (MLX5_CAP_GEN(mdev, num_q_monitor_counters) < in mlx5e_monitor_counter_supported()
103 int max_num_of_counters = MLX5_CAP_GEN(mdev, max_num_of_monitor_counters); in mlx5e_set_monitor_counter()
104 int num_q_counters = MLX5_CAP_GEN(mdev, num_q_monitor_counters); in mlx5e_set_monitor_counter()
106 MLX5_CAP_GEN(mdev, num_ppcnt_monitor_counters); in mlx5e_set_monitor_counter()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/lag/
H A Dlag.h118 if (!MLX5_CAP_GEN(dev, vport_group_manager) || in mlx5_lag_is_supported()
119 !MLX5_CAP_GEN(dev, lag_master) || in mlx5_lag_is_supported()
120 MLX5_CAP_GEN(dev, num_lag_ports) < 2 || in mlx5_lag_is_supported()
121 MLX5_CAP_GEN(dev, num_lag_ports) > MLX5_MAX_PORTS) in mlx5_lag_is_supported()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dktls.h25 if (!MLX5_CAP_GEN(mdev, tls_tx) && !MLX5_CAP_GEN(mdev, tls_rx)) in mlx5e_is_ktls_device()
28 if (!MLX5_CAP_GEN(mdev, log_max_dek)) in mlx5e_is_ktls_device()
64 return !is_kdump_kernel() && MLX5_CAP_GEN(mdev, tls_tx); in mlx5e_is_ktls_tx()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Ddr_cmd.c117 caps->prio_tag_required = MLX5_CAP_GEN(mdev, prio_tag_required); in mlx5dr_cmd_query_device()
118 caps->eswitch_manager = MLX5_CAP_GEN(mdev, eswitch_manager); in mlx5dr_cmd_query_device()
119 caps->gvmi = MLX5_CAP_GEN(mdev, vhca_id); in mlx5dr_cmd_query_device()
120 caps->flex_protocols = MLX5_CAP_GEN(mdev, flex_parser_protocols); in mlx5dr_cmd_query_device()
121 caps->sw_format_ver = MLX5_CAP_GEN(mdev, steering_format_version); in mlx5dr_cmd_query_device()
123 MLX5_CAP_GEN(mdev, fl_rc_qp_when_roce_disabled); in mlx5dr_cmd_query_device()
125 if (MLX5_CAP_GEN(mdev, roce)) { in mlx5dr_cmd_query_device()
137 caps->isolate_vl_tc = MLX5_CAP_GEN(mdev, isolate_vl_tc_new); in mlx5dr_cmd_query_device()
145 MLX5_CAP_GEN(mdev, log_header_modify_argument_granularity); in mlx5dr_cmd_query_device()
147 MLX5_CAP_GEN(mdev, log_header_modify_argument_max_alloc); in mlx5dr_cmd_query_device()
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
H A Degress_ofld.c77 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) { in esw_acl_egress_ofld_rules_create()
125 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) { in esw_acl_egress_ofld_groups_create()
192 !MLX5_CAP_GEN(esw->dev, prio_tag_required)) in esw_acl_egress_ofld_setup()
202 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) in esw_acl_egress_ofld_setup()
259 fwd_dest.vport.vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id); in mlx5_esw_acl_egress_vport_bond()
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/
H A Ddev.c30 return MLX5_CAP_GEN(dev, sf) && mlx5_vhca_event_supported(dev); in mlx5_sf_dev_supported()
274 if (MLX5_CAP_GEN(table->dev, eswitch_manager)) in mlx5_sf_dev_queue_active_work()
313 if (MLX5_CAP_GEN(dev, max_num_sf)) in mlx5_sf_dev_table_create()
314 max_sfs = MLX5_CAP_GEN(dev, max_num_sf); in mlx5_sf_dev_table_create()
316 max_sfs = 1 << MLX5_CAP_GEN(dev, log_max_sf); in mlx5_sf_dev_table_create()
317 table->sf_bar_length = 1 << (MLX5_CAP_GEN(dev, log_min_sf_size) + 12); in mlx5_sf_dev_table_create()
/openbmc/linux/include/linux/mlx5/
H A Ddriver.h1241 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); in mlx5_core_is_ecpf_esw_manager()
1261 return MLX5_CAP_GEN(dev, vport_group_manager) && in mlx5_lag_is_lacp_owner()
1262 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) && in mlx5_lag_is_lacp_owner()
1263 MLX5_CAP_GEN(dev, lag_master); in mlx5_lag_is_lacp_owner()
1288 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && in mlx5_core_is_mp_slave()
1289 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; in mlx5_core_is_mp_slave()
1294 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; in mlx5_core_is_mp_master()
1308 return MLX5_CAP_GEN(dev, native_port_num); in mlx5_core_native_port_num()
1313 int idx = MLX5_CAP_GEN(dev, native_port_num); in mlx5_get_dev_index()
1329 if (MLX5_CAP_GEN(dev, roce_rw_supported)) in mlx5_get_roce_state()
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