Searched refs:MISC_CLK_CTRL__ZCLK_SEL__SHIFT (Results 1 – 12 of 12) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | fiji_baco.c | 94 …DIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x…
|
| H A D | polaris_baco.c | 97 …DIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x…
|
| H A D | ci_baco.c | 112 …DIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x…
|
| H A D | tonga_baco.c | 103 …DIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x…
|
| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | cik.c | 1818 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); in cik_program_aspm()
|
| H A D | vi.c | 1199 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); in vi_program_aspm()
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| H A D | smu_7_0_0_sh_mask.h | 272 #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 macro
|
| H A D | smu_7_1_1_sh_mask.h | 270 #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 macro
|
| H A D | smu_7_0_1_sh_mask.h | 270 #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 macro
|
| H A D | smu_7_1_0_sh_mask.h | 268 #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 macro
|
| H A D | smu_7_1_3_sh_mask.h | 298 #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 macro
|
| H A D | smu_7_1_2_sh_mask.h | 270 #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 macro
|