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Searched refs:MCIF_WB_BUFMGR_VCE_CONTROL (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.c199 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1); in mmhubbub2_config_mcif_arb()
217 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, params->vce_int_en); in mmhubbub2_config_mcif_irq()
219 …REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, params->vce_slice_int_en); in mmhubbub2_config_mcif_irq()
H A Ddcn20_mmhubbub.h65 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
447 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h56 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
107 SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
355 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
356 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
H A Ddcn30_mmhubbub.c206 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1); in mmhubbub3_config_mcif_arb()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h76 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
239 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_mmhubbub.h56 SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
170 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
H A Ddcn32_mmhubbub.c206 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1); in mmhubbub32_config_mcif_arb()
H A Ddcn32_resource.h716 SRI2_ARR(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst), \