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Searched refs:MASK_ALL_BITS (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training.c121 {0x1034, 0x38000, MASK_ALL_BITS},
122 {0x1038, 0x0, MASK_ALL_BITS},
123 {0x10b0, 0x0, MASK_ALL_BITS},
124 {0x10b8, 0x0, MASK_ALL_BITS},
125 {0x10c0, 0x0, MASK_ALL_BITS},
126 {0x10f0, 0x0, MASK_ALL_BITS},
127 {0x10f4, 0x0, MASK_ALL_BITS},
128 {0x10f8, 0xff, MASK_ALL_BITS},
129 {0x10fc, 0xffff, MASK_ALL_BITS},
130 {0x1130, 0x0, MASK_ALL_BITS},
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H A Dddr3_training_bist.c46 …ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_length, MASK_ALL_BITS… in ddr3_tip_bist_activate()
56 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_OFFS_REG, offset, MASK_ALL_BITS); in ddr3_tip_bist_activate()
66 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_bist_activate()
88 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
94 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
101 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
107 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
237 ddr3_tip_if_read(0, ACCESS_TYPE_UNICAST, 0, reg_map[subphy], &read_data, MASK_ALL_BITS); in mv_ddr_tip_bist()
434 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_bist_tx()
467 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_len, MASK_ALL_BITS); in mv_ddr_odpg_bist_prepare()
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H A Dddr3_training_leveling.c67 MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
110 MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
196 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_read_leveling()
253 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
262 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
296 MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
441 MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
484 MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
568 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_per_bit_read_leveling()
609 MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
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H A Dddr3_training_ip_engine.c416 MASK_ALL_BITS)); in ddr3_tip_ip_training()
563 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_ip_training()
588 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
594 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
601 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
607 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
612 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
617 ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
799 MASK_ALL_BITS)); in ddr3_tip_read_training_result()
893 ODPG_DATA_CTRL_REG, reg_data, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
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H A Dmv_ddr_plat.c250 if (mask != MASK_ALL_BITS) { in dunit_write()
251 dunit_read(addr, MASK_ALL_BITS, &reg_val); in dunit_write()
291 dunit_read(ODPG_ENABLE_REG, MASK_ALL_BITS, &data); in mv_ddr_is_odpg_done()
334 dunit_read(DRAM_INIT_CTRL_STATUS_REG, MASK_ALL_BITS, &data); in mv_ddr_is_training_done()
582 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, &reg_val); in is_prfa_done()
602 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val); in prfa_write()
604 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val); in prfa_write()
626 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, &reg_val); in prfa_read()
632 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, &reg_val); in prfa_read()
H A Dddr3_training_pbs.c64 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
75 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS); in ddr3_tip_pbs()
107 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
226 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
415 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
537 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
640 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
872 MASK_ALL_BITS)); in ddr3_tip_pbs()
878 ODPG_WR_RD_MODE_ENA_REG, 0xffff, MASK_ALL_BITS)); in ddr3_tip_pbs()
H A Dddr3_debug.c126 MASK_ALL_BITS)); in ddr3_tip_reg_dump()
549 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
554 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
559 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
591 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
991 reg, MASK_ALL_BITS); in ddr3_tip_run_sweep_test()
1079 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS); in ddr3_tip_run_sweep_test()
1137 CTX_PHY_REG(cs), MASK_ALL_BITS); in ddr3_tip_run_leveling_sweep_test()
1200 MASK_ALL_BITS)); in ddr3_tip_run_leveling_sweep_test()
1273 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS); in ddr3_tip_run_leveling_sweep_test()
H A Dddr3_training_ip_def.h41 #define MASK_ALL_BITS 0xffffffff macro
H A Dddr3_training_centralization.c85 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
485 MASK_ALL_BITS)); in ddr3_tip_centralization()
523 MASK_ALL_BITS)); in ddr3_tip_special_rx()
H A Dddr3_training_hw_algo.c60 data_read, MASK_ALL_BITS)); in ddr3_tip_write_additional_odt_setting()