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Searched refs:LVL_1_INST (Results 1 – 1 of 1) sorted by relevance

/openbmc/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c30 #define LVL_1_INST 1 macro
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
73 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
828 case LVL_1_INST: in init_intel_cacheinfo()