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/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
82 | PCH-LPC | | Devices | | Devices |
129 PCH-LPC::
157 - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Drtc-st-lpc.txt1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
48 | PCH-LPC | | Devices | | Devices |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
80 | PCH-LPC | | Devices | | Devices |
127 PCH-LPC::
159 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
/openbmc/linux/drivers/soc/aspeed/
H A DKconfig8 tristate "ASPEED LPC firmware cycle control"
13 Control LPC firmware cycle mappings through ioctl()s. The driver
15 host LPC read/write region can be buffered.
18 tristate "ASPEED LPC snoop support"
23 Provides a driver to control the LPC snoop interface which
25 the host to an arbitrary LPC I/O port.
/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md1 # Management Component Transport Protocol (MCTP) LPC Transport Binding Specification for ASPEED BMC…
6 host and BMC over the LPC bus on ASPEED BMC platforms.
17 2. Intel (R) Low Pin Count (LPC) Interface Specification 1.1,
52 ### LPC Bus: Low Pin Count Bus
57 ### LPC FW: LPC Firmware Cycles
59 LPC firmware cycles allow separate boot BIOS firmware memory cycles and
60 application memory cycles with respect to the LPC bus. The ASPEED BMCs allow
61 remapping of the LPC firmware cycles onto arbitrary regions of the BMC's
94 ## MCTP over LPC Transport
101 - A window of the LPC FW address space, where reads and writes are forwarded to
[all …]
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-driver-aspeed-vuart5 will appear on the host <-> BMC LPC bus.
13 the UART will appear on the host <-> BMC LPC bus.
21 host via the BMC LPC bus.
/openbmc/hiomapd/Documentation/
H A Dmboxd.md29 lpc.c - Contains the functions for controlling the LPC bus mapping
44 currently suspended and the LPC bus maps the flash
47 currently suspended and the LPC bus maps the flash
50 currently suspended and the LPC bus maps the reserved
53 currently suspended and the LPC bus maps the reserved
90 it at the correct LPC offset for that windows location and the requested flash
97 this window and the host pointed at its location on the LPC bus.
131 After initilisation, the daemon points the LPC mapping to the actual flash
168 SIGHUP - Clear the window cache and point the LPC bus mapping back to
179 the active window has been closed, points the LPC bus mapping back to flash,
H A Dprotocol.md33 flash data in the LPC firmware space, communicated via functions in the LPC IO
52 2. Remapping of LPC Firmware cycles onto the AHB (LPC2AHB bridge)
64 The core concept of the protocol moves access away from the naive routing of LPC
66 on servicing the LPC firmware cycles from reserved system memory. As the memory
75 The original transport for the protocol was the ASPEED BMC LPC mailbox
88 which adjusts the mapping of the LPC firmware space as requested and returns a
109 …nd) | ✓ | ✓ | ✓ | Reset the state of the LPC firmware space, clo…
140 1. The [ASPEED BMC LPC Mailbox transport](#mailbox-transport)
146 design is limited by the most constrained transport - the LPC mailbox
182 the associated LPC firmware cycles to write the regions into the erased state.
[all …]
/openbmc/phosphor-mboxd/Documentation/
H A Dmboxd.md30 mboxd_lpc.c - Contains the functions for controlling the LPC bus mapping
45 currently suspended and the LPC bus maps the flash
48 currently suspended and the LPC bus maps the flash
51 currently suspended and the LPC bus maps the reserved
54 currently suspended and the LPC bus maps the reserved
91 it at the correct LPC offset for that windows location and the requested flash
98 this window and the host pointed at its location on the LPC bus.
132 After initilisation, the daemon points the LPC mapping to the actual flash
169 SIGHUP - Clear the window cache and point the LPC bus mapping back to
180 active window has been closed, points the LPC bus mapping back to flash, clears
/openbmc/linux/drivers/net/ethernet/nxp/
H A DKconfig3 tristate "NXP ethernet MAC on LPC devices"
9 some NXP LPC devices. You can safely enable this option for LPC32xx
/openbmc/openbmc-test-automation/oem/nuvoton/
H A Dtest_ipmi_flash.robot31 Get LPC SHM Address
37 Get LPC SHM Address
49 Get LPC SHM Address
63 Get LPC SHM Address
75 Get LPC SHM Address
102 Get LPC SHM Address
103 [Documentation] Get Mapped Address of LPC hare Memory.
/openbmc/linux/drivers/mcb/
H A DKconfig33 tristate "LPC (non PCI) based MCB carrier"
37 This is a MCB carrier on a LPC or non PCI device.
/openbmc/u-boot/arch/arm/mach-aspeed/
H A DKconfig23 which is enabled by support of LPC and eSPI peripherals.
32 which is enabled by support of LPC and eSPI peripherals.
45 which is enabled by support of LPC and eSPI peripherals.
/openbmc/docs/designs/
H A Dfirmware-update-via-blobs.md25 1. IPMI over LPC
27 1. LPC Memory-Mapped Region
51 the P2A bridge and what region to use or whether to turn on the LPC memory map
223 #### LPC Sequence
226 1. WriteMeta (specify region information from host for LPC)
231 1. WriteMeta (LPC Region)
232 1. SessionStat (verify LPC config)
280 lpc = (1 << 10), /* Expect to send contents over LPC bridge. */
324 ##### If LPC
471 aimed at LPC which needs to be told the memory address so it can configure the
[all …]
H A Dbmc-service-failure-debug-and-recovery.md239 2. LPC
246 recognise it is in a bad state. PCIe and LPC are preferable by comparison as the
248 over either interface. Comparatively, PCIe is more complex than LPC, so an
249 LPC-based approach is preferred.
251 The host already makes use of several LPC peripherals exposed from the BMC:
253 1. Mapped LPC FW cycles
256 4. A KCS device for a vendor-defined MCTP LPC binding
258 The host could take advantage of any of the following LPC peripherals for
262 2. The LPC mailbox
265 In ASPEED BMC SoCs prior to the AST2600 the LPC mailbox required configuration
[all …]
/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dintel-lpc.txt1 Intel LPC Device Binding
14 the LPC device
/openbmc/phosphor-ipmi-flash/
H A Dmeson.build67 # Enable LPC and PCI for tests only.
72 'Invalid configuration enabling both PCI and LPC.',
122 summary(option_key, option_value, section: 'Enabled LPC Features')
/openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/
H A Dlpc.asl6 /* Intel LPC Bus Device - 0:1f.0 */
102 /* LPC device: Resource consumption */
/openbmc/openbmc/meta-openpower/recipes-phosphor/host/aspeed-lpc-ctrl/
H A Dpnorboot.service2 Description=ASPEED LPC boot from PNOR
/openbmc/phosphor-host-postd/
H A Dlpcsnoop.service.in2 Description=LPC Snoop Daemon
H A DREADME.md1 # LPC Snoop Broadcast Daemon
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7757.c803 LPC, LPC5, LPC6, LPC7, LPC8, enumerator
868 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
869 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
870 INTC_VECT(LPC, 0xb20),
966 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
1066 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
/openbmc/u-boot/board/google/
H A DKconfig19 solid state drive. There is a Chrome OS EC connected on LPC,
52 Chrome OS EC connected on LPC, and it provides a 2560x1700 high

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