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Searched refs:LCCR0 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/video/fbdev/
H A Dsa1100fb.c703 if (readl_relaxed(fbi->base + LCCR0) != fbi->reg_lccr0 || in sa1100fb_activate_var()
796 writel_relaxed(fbi->reg_lccr0 & ~LCCR0_LEN, fbi->base + LCCR0); in sa1100fb_enable_controller()
799 writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0); in sa1100fb_enable_controller()
806 dev_dbg(fbi->dev, "LCCR0: 0x%08x\n", readl_relaxed(fbi->base + LCCR0)); in sa1100fb_enable_controller()
828 lccr0 = readl_relaxed(fbi->base + LCCR0); in sa1100fb_disable_controller()
830 writel_relaxed(lccr0, fbi->base + LCCR0); in sa1100fb_disable_controller()
832 writel_relaxed(lccr0, fbi->base + LCCR0); in sa1100fb_disable_controller()
850 u32 lccr0 = readl_relaxed(fbi->base + LCCR0) | LCCR0_LDM; in sa1100fb_handle_irq()
851 writel_relaxed(lccr0, fbi->base + LCCR0); in sa1100fb_handle_irq()
H A Dsa1100fb.h15 #define LCCR0 0x0000 /* LCD Control Reg. 0 */ macro
H A Dpxafb.c1153 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); in pxafb_smart_flush()
1185 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); in pxafb_smart_flush()
1195 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); in pxafb_smart_flush()
1391 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) || in pxafb_activate_var()
1465 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); in pxafb_enable_controller()
1470 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); in pxafb_enable_controller()
1488 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM; in pxafb_disable_controller()
1489 lcd_writel(fbi, LCCR0, lccr0); in pxafb_disable_controller()
1490 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS); in pxafb_disable_controller()
1508 lccr0 = lcd_readl(fbi, LCCR0); in pxafb_handle_irq()
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H A Dpxa3xx-regs.h8 #define LCCR0 (0x000) /* LCD Controller Control Register 0 */ macro
/openbmc/u-boot/drivers/video/
H A Dpxa_lcd.c500 writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); in pxafb_enable_controller()
503 writel(readl(LCCR0) | LCCR0_ENB, LCCR0); in pxafb_enable_controller()
513 debug("LCCR0 = 0x%08x\n", readl(LCCR0)); in pxafb_enable_controller()
/openbmc/linux/Documentation/fb/
H A Dsa1100fb.rst22 displays are supported as long as the SDS bit is set in LCCR0; GPIO<9:2>
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2091 #define LCCR0 0x44000000 /* LCD Controller Control Register 0 */ macro
/openbmc/u-boot/include/
H A DSA-1100.h2665 #define LCCR0 /* LCD Control Reg. 0 */ \ macro