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Searched refs:L1CSR2_DCWS (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S233 oris r3,r3,(L1CSR2_DCWS)@h
245 andis. r3,r3,(L1CSR2_DCWS)@h
H A Dcpu_init.c774 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); in cpu_init_r()
790 if (mfspr(L1CSR2) & L1CSR2_DCWS) in cpu_init_r()
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h594 #define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */ macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h498 #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ macro
/openbmc/linux/arch/powerpc/kernel/
H A Dtraps.c656 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) in machine_check_e500mc()