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Searched refs:IS_DG2 (Results 1 – 25 of 36) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_ccs_mode.c17 if (!IS_DG2(gt->i915)) in intel_gt_apply_ccs_mode()
H A Dintel_workarounds.c921 else if (IS_DG2(i915)) in __intel_engine_init_ctx_wa()
1375 if (IS_DG2(gt->i915)) in xehp_init_mcr()
1710 if (IS_DG2(gt->i915)) { in gt_tuning_settings()
1736 else if (IS_DG2(i915)) in gt_init_workarounds()
2209 else if (IS_DG2(i915)) in intel_engine_init_whitelist()
2319 IS_DG2(i915)) { in rcs_engine_wa_init()
2326 IS_DG2(i915)) { in rcs_engine_wa_init()
2332 if (IS_DG2(i915)) { in rcs_engine_wa_init()
2349 if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()
2812 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915)) in add_render_compute_tuning_settings()
[all …]
H A Dintel_gt_mcr.c189 } else if (IS_DG2(i915)) { in intel_gt_mcr_init()
636 *group = IS_DG2(gt->i915) ? 1 : 0; in get_nonterminated_steering()
H A Dgen8_engine_cs.c230 IS_DG2(rq->i915)) { in mtl_dummy_pipe_control()
822 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915)) in gen12_emit_fini_breadcrumb_rcs()
H A Dintel_gsc.c192 } else if (IS_DG2(i915)) { in gsc_init_one()
H A Dintel_mocs.c511 } else if (IS_DG2(i915)) { in get_mocs_settings()
H A Dintel_reset.c648 if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES) in gen8_reset_engines()
H A Dintel_lrc.c1352 IS_DG2(ce->engine->i915)) in gen12_emit_indirect_ctx_rcs()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_hwmon.c291 if (IS_DG1(i915) || IS_DG2(i915)) in hwm_pcode_read_i1()
311 return IS_DG1(i915) || IS_DG2(i915) ? 0444 : 0; in hwm_in_is_visible()
736 if (IS_DG1(i915) || IS_DG2(i915)) { in hwm_get_preregistration_info()
H A Di915_drv.h572 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) macro
689 (IS_DG2(__i915) && \
H A Dintel_clock_gating.c842 else if (IS_DG2(i915)) in intel_clock_gating_hooks_init()
H A Di915_perf.c2900 if (IS_XEHPSDV(i915) || IS_DG2(i915)) { in gen12_enable_metric_set()
2980 if (IS_XEHPSDV(i915) || IS_DG2(i915)) { in gen12_disable_metric_set()
3228 if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { in i915_perf_oa_timestamp_frequency()
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_huc.c308 if (IS_DG2(i915)) { in intel_huc_init_early()
356 if (IS_DG2(gt->i915)) { in check_huc_loading_mode()
H A Dintel_guc.c277 IS_DG2(gt->i915)) in guc_ctl_wa_flags()
287 if (IS_DG2(gt->i915)) in guc_ctl_wa_flags()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c1495 if (IS_DG2(dev_priv)) in bxt_de_pll_readout()
1843 return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) && in pll_enable_wa_needed()
1912 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()
1948 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) in bxt_set_cdclk()
2268 if (!IS_DG2(i915)) in intel_pcode_notify()
2463 if (IS_DG2(i915)) in intel_set_cdclk_pre_plane_update()
2508 if (IS_DG2(i915)) in intel_set_cdclk_post_plane_update()
2648 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()
3056 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); in intel_cdclk_need_serialize()
3597 } else if (IS_DG2(dev_priv)) { in intel_init_cdclk_hooks()
H A Dintel_display_device.h45 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
H A Dintel_dmc.c375 if (IS_DG2(i915)) { in get_flip_queue_event_regs()
1043 } else if (IS_DG2(i915)) { in intel_dmc_init()
H A Dintel_display_power.c950 if (IS_DG2(dev_priv)) in get_allowed_dc_mask()
1696 if (IS_DG2(dev_priv)) in icl_display_core_init()
H A Dintel_ddi_buf_trans.c1714 } else if (IS_DG2(i915)) { in intel_ddi_buf_trans_init()
H A Dintel_bw.c668 else if (IS_DG2(dev_priv)) in intel_bw_init_hw()
H A Dintel_display_power_map.c1657 else if (IS_DG2(i915)) in intel_display_power_map_init()
H A Dintel_ddi.c216 } else if (IS_DG2(dev_priv)) { in intel_wait_ddi_buf_active()
4868 } else if (IS_DG2(dev_priv)) { in intel_ddi_init()
4930 } else if (IS_DG2(dev_priv)) { in intel_ddi_init()
H A Dintel_fbc.c818 if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915)) in intel_fbc_program_workarounds()
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_pch.c225 } else if (IS_DG2(dev_priv)) { in intel_detect_pch()
H A Dintel_dram.c662 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) in intel_dram_detect()

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