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Searched refs:ISB (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/
H A Dbarriers.h33 #define ISB asm volatile ("isb sy" : : : "memory") macro
37 #define ISB CP15ISB macro
41 #define ISB asm volatile ("" : : : "memory") macro
46 #define isb() ISB
/openbmc/qemu/tests/tcg/multiarch/
H A Dtest-aes-main.c.inc152 verify(&rounds[i].start, &t, "ISB+ISR");
166 verify(&rounds[i - 1].after_sr, &t, "ISB+ISR+AK+IMC");
178 verify(&rounds[i - 1].after_sr, &t, "ISB+ISR+IMC+AK");
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/mozjs/mozjs-115/
H A Darmv5.patch1 The ISB instruction isn't available in ARMv5 or v6, so
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcache.c36 ISB; in enable_ca7_smp()
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S141 mcr p15, 0, r0, c7, c5, 4 @ ISB
186 mcr p15, 0, r0, c7, c5, 4 @ ISB
265 isb @ Recommended ISB after l2actlr update
/openbmc/linux/arch/arm/mm/
H A Dproc-v6.S63 mcr p15, 0, r1, c7, c5, 4 @ ISB
172 mcr p15, 0, ip, c7, c5, 4 @ ISB
/openbmc/qemu/target/arm/tcg/
H A Da32-uncond.decode52 ISB 1111 0101 0111 1111 1111 0000 0110 ----
H A Dt32.decode392 ISB 1111 0011 1011 1111 1000 1111 0110 ----
H A Da64.decode248 ISB 1101 0101 0000 0011 0011 ---- 110 11111
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S898 mcr p15, 0, r0, c7, c5, 4 @ ISB
902 mcr p15, 0, r0, c7, c5, 4 @ ISB
1202 mcr p15, 0, r0, c7, c5, 4 @ ISB
1284 mcr p15, 0, r10, c7, c5, 4 @ ISB
/openbmc/linux/arch/arm64/
H A DKconfig983 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
984 two ISB instructions if no ERET is to take place.
1103 Instruction Synchronization Barrier (ISB) after kernel changes to
1173 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1256 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1771 strongly recommended to use the ISB, DSB, and DMB
/openbmc/linux/arch/arm/
H A DKconfig835 to deadlock. This workaround puts DSB before executing ISB if