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Searched refs:ISA_MIPS_R5 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dmips-defs.h22 #define ISA_MIPS_R5 0x0000000000000100ULL macro
78 #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5)
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c8622 check_insn(ctx, ISA_MIPS_R5); in gen_cp0()