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Searched refs:IP_VER (Results 1 – 25 of 42) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_mcr.c166 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { in intel_gt_mcr_init()
168 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in intel_gt_mcr_init()
169 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) in intel_gt_mcr_init()
202 GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) { in intel_gt_mcr_init()
254 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) { in rw_with_mcr_steering_fw()
314 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70) && rw_flag == FW_REG_WRITE) in rw_with_mcr_steering_fw()
316 else if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70)) in rw_with_mcr_steering_fw()
378 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_lock()
434 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_unlock()
500 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_multicast_write()
[all …]
H A Dintel_workarounds.c798 if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in xelpg_ctx_gt_tuning_init()
799 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))) in xelpg_ctx_gt_tuning_init()
810 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in xelpg_ctx_workarounds_init()
811 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { in xelpg_ctx_workarounds_init()
891 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in gen12_ctx_gt_fake_wa_init()
917 if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) in __intel_engine_init_ctx_wa()
1655 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in xelpg_gt_workarounds_init()
1656 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { in xelpg_gt_workarounds_init()
1699 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { in gt_tuning_settings()
1732 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) in gt_init_workarounds()
[all …]
H A Dgen8_engine_cs.c229 if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) || in mtl_dummy_pipe_control()
271 if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) in gen12_emit_flush_rcs()
822 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915)) in gen12_emit_fini_breadcrumb_rcs()
827 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) in gen12_emit_fini_breadcrumb_rcs()
H A Dintel_gt.h22 BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
61 return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type == GT_MEDIA; in intel_gt_needs_wa_22016122933()
H A Dintel_lrc.c694 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) in reg_offsets()
696 else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in reg_offsets()
698 else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in reg_offsets()
709 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in reg_offsets()
722 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in lrc_ring_mi_mode()
736 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in lrc_ring_bb_offset()
751 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in lrc_ring_gpr0()
798 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in lrc_ring_cmd_buf_cctl()
1350 if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in gen12_emit_indirect_ctx_rcs()
1351 IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) || in gen12_emit_indirect_ctx_rcs()
H A Dintel_engine_cs.c769 if (MEDIA_VER_FULL(i915) < IP_VER(12, 50)) in engine_mask_apply_media_fuses()
776 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) { in engine_mask_apply_media_fuses()
852 if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) && in engine_mask_apply_copy_fuses()
853 GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))) in engine_mask_apply_copy_fuses()
1216 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) { in intel_engine_init_tlb_invalidation()
1221 if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) || in intel_engine_init_tlb_invalidation()
1222 GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) || in intel_engine_init_tlb_invalidation()
1223 GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) || in intel_engine_init_tlb_invalidation()
1224 GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) { in intel_engine_init_tlb_invalidation()
1227 } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) || in intel_engine_init_tlb_invalidation()
[all …]
H A Dintel_gt_mcr.h56 GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
H A Dintel_mocs.c498 if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) { in get_mocs_settings()
673 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) in init_l3cc_table()
H A Dintel_reset.c290 loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1; in gen6_hw_domain_reset()
708 if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0)) in needs_wa_14015076503()
1644 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) in intel_engine_reset_needs_wa_22011802037()
1647 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_engine_reset_needs_wa_22011802037()
H A Dintel_gtt.c649 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) in setup_private_pat()
651 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) in setup_private_pat()
H A Dintel_rc6.c126 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) in gen11_rc6_enable()
H A Dintel_gt.c265 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { in intel_gt_clear_error_registers()
389 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) in intel_gt_check_and_clear_faults()
H A Dintel_sseu.c645 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) in intel_sseu_info_init()
854 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { in intel_sseu_print_topology()
H A Dintel_migrate.c928 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) in emit_clear()
939 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { in emit_clear()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_getparam.c163 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) in i915_getparam_ioctl()
172 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) in i915_getparam_ioctl()
H A Di915_drv.h425 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) macro
428 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
434 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
848 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
H A Dintel_device_info.c311 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel)) in ip_ver_read()
H A Dintel_uncore.c2317 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) in intel_uncore_fw_domains_init()
2497 if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) in intel_uncore_setup_mmio()
2572 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { in uncore_forcewake_init()
2576 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) { in uncore_forcewake_init()
2580 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { in uncore_forcewake_init()
2584 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { in uncore_forcewake_init()
2734 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) { in intel_uncore_prune_engine_fw_domains()
H A Di915_perf.c294 #define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
833 GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 50)) { in gen8_append_oa_reports()
1447 } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) { in gen12_get_render_context_id()
3228 if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { in i915_perf_oa_timestamp_frequency()
4151 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) { in read_properties_unlocked()
4518 GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70)) in mtl_is_valid_oam_b_counter_addr()
4533 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70)) in gen12_is_valid_mux_addr()
4894 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) { in __oam_engine_group()
4967 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in oa_init_groups()
H A Di915_irq.c1323 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_handler()
1348 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_reset()
1373 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_postinstall()
H A Di915_debugfs.c147 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) { in i915_cache_level_str()
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_hwconfig.c99 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in has_table()
H A Dintel_guc_fw.c29 if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50)) in guc_prepare_xfer()
H A Dintel_guc.c272 GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50)) in guc_ctl_wa_flags()
276 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in guc_ctl_wa_flags()
H A Dintel_guc_ads.c391 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in guc_mmio_regset_init()
501 #define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) ? \

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