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Searched refs:INTR_ENABLE (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/hw/ssi/
H A Dibex_spi_host.c40 REG32(INTR_ENABLE, 0x04)
41 FIELD(INTR_ENABLE, ERROR, 0, 1)
42 FIELD(INTR_ENABLE, SPI_EVENT, 1, 1)
180 bool error_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR); in ibex_spi_host_irq()
181 bool event_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT); in ibex_spi_host_irq()
/openbmc/qemu/hw/timer/
H A Dibex_timer.c48 REG32(INTR_ENABLE, 0x114)
49 FIELD(INTR_ENABLE, IE_0, 0, 1)
/openbmc/linux/drivers/block/
H A Dswim3.c96 #define INTR_ENABLE 0x01 macro
940 out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE); in floppy_open()
981 out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE); in floppy_open()
/openbmc/linux/drivers/net/ethernet/
H A Djme.c373 jwrite32(jme, JME_IENS, INTR_ENABLE); in jme_start_irq()
382 jwrite32f(jme, JME_IENC, INTR_ENABLE); in jme_stop_irq()
1497 jwrite32f(jme, JME_IENC, INTR_ENABLE); in jme_intr_msi()
1549 jwrite32f(jme, JME_IENS, INTR_ENABLE); in jme_intr_msi()
1564 if (unlikely((intrstat & INTR_ENABLE) == 0)) in jme_intr()
H A Djme.h1069 static const u32 INTR_ENABLE = INTR_SWINTR | variable
/openbmc/qemu/hw/char/
H A Dibex_uart.c44 REG32(INTR_ENABLE, 0x04)
/openbmc/linux/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c74 #define INTR_ENABLE 0x0114 macro
799 cdns_ctrl->reg + INTR_ENABLE); in cadence_nand_set_irq_mask()
2873 writel_relaxed(INTR_ENABLE_INTR_EN, cdns_ctrl->reg + INTR_ENABLE); in cadence_nand_irq_cleanup()
/openbmc/linux/drivers/scsi/qla4xxx/
H A Dql4_fw.h376 #define INTR_ENABLE 1 macro
H A Dql4_nx.c4099 mbox_cmd[1] = INTR_ENABLE; in qla4_8xxx_intr_enable()