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Searched refs:IMX6SX_CLK_PLL4_POST_DIV (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6sx-clock.h44 #define IMX6SX_CLK_PLL4_POST_DIV 31 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dimx6sx-clock.h40 #define IMX6SX_CLK_PLL4_POST_DIV 31 macro
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx-sabreauto.dts115 <&clks IMX6SX_CLK_PLL4_POST_DIV>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sx.c247 hws[IMX6SX_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", in imx6sx_clocks_init()