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Searched refs:IMX6SLL_CLK_PLL1_SW (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6sll-clock.h65 #define IMX6SLL_CLK_PLL1_SW 52 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dimx6sll-clock.h63 #define IMX6SLL_CLK_PLL1_SW 52 macro
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sll.dtsi70 <&clks IMX6SLL_CLK_PLL1_SW>,
145 <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>,
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sll.c195 …hws[IMX6SLL_CLK_PLL1_SW] = imx_clk_hw_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, A… in imx6sll_clocks_init()
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll.dtsi71 <&clks IMX6SLL_CLK_PLL1_SW>,