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Searched refs:IDC_CERR2 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcpu.c118 while (!((m = rd_ic_cst()) & IDC_CERR2)) { in checkicache()
158 while (!((m = rd_dc_cst()) & IDC_CERR2)) { in checkdcache()
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_8xx.h77 #define IDC_CERR2 0x00100000 /* Cache error 2 */ macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcache.h105 #define IDC_CERR2 0x00100000 /* Cache error 2 */ macro