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Searched refs:ICPU_MEMCTRL_TIMING1 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h134 #define ICPU_MEMCTRL_TIMING1 0x24c macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h145 #define ICPU_MEMCTRL_TIMING1 0x128 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h148 #define ICPU_MEMCTRL_TIMING1 0x120 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h153 #define ICPU_MEMCTRL_TIMING1 0x128 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h155 #define ICPU_MEMCTRL_TIMING1 0x148 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h788 writel(MSCC_MEMPARM_TIMING1, BASE_CFG + ICPU_MEMCTRL_TIMING1); in hal_vcoreiii_init_memctl()