Searched refs:HW_SSP_CTRL0 (Results 1 – 3 of 3) sorted by relevance
91 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer() 110 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0 in mxs_spi_cs_to_reg() 113 * in HW_SSP_CTRL0 register do have multiple usage, please refer to in mxs_spi_cs_to_reg() 192 ctrl0 = readl(ssp->base + HW_SSP_CTRL0); in mxs_spi_txrx_dma() 306 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio() 311 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio() 315 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio() 317 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio() 324 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio() 327 ssp->base + HW_SSP_CTRL0 in mxs_spi_txrx_pio() [all...]
19 #define HW_SSP_CTRL0 0x000 macro
115 writel(ctrl0, ssp->base + HW_SSP_CTRL0); in mxs_mmc_reset()521 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()526 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_mmc_enable_sdio_irq()